From patchwork Sun Sep 25 19:55:43 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 116323 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 484E0B71C2 for ; Mon, 26 Sep 2011 06:20:59 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 275EA282D4; Sun, 25 Sep 2011 21:55:52 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uhsP3smPCPuu; Sun, 25 Sep 2011 21:55:51 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 91316282BF; Sun, 25 Sep 2011 21:55:50 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4619E282BF for ; Sun, 25 Sep 2011 21:55:49 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1HTmLZytZR0Q for ; Sun, 25 Sep 2011 21:55:48 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-bw0-f44.google.com (mail-bw0-f44.google.com [209.85.214.44]) by theia.denx.de (Postfix) with ESMTPS id 2E2E6282A2 for ; Sun, 25 Sep 2011 21:55:47 +0200 (CEST) Received: by bkaq10 with SMTP id q10so4698321bka.3 for ; Sun, 25 Sep 2011 12:55:47 -0700 (PDT) Received: by 10.204.132.133 with SMTP id b5mr3839788bkt.343.1316980546970; Sun, 25 Sep 2011 12:55:46 -0700 (PDT) Received: from mashiro.ms.mff.cuni.cz (eduroam32.ms.mff.cuni.cz. [195.113.21.32]) by mx.google.com with ESMTPS id z7sm18359663bkt.5.2011.09.25.12.55.46 (version=SSLv3 cipher=OTHER); Sun, 25 Sep 2011 12:55:46 -0700 (PDT) From: Marek Vasut To: u-boot@lists.denx.de Date: Sun, 25 Sep 2011 21:55:43 +0200 Message-Id: <1316980543-27029-1-git-send-email-marek.vasut@gmail.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1316428941-8957-3-git-send-email-marek.vasut@gmail.com> References: <1316428941-8957-3-git-send-email-marek.vasut@gmail.com> Subject: [U-Boot] [PATCH 2/2 V2] EfikaSB: Add preliminary EfikaSB support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Marek Vasut Cc: Stefano Babic --- board/efikamx/efikamx.c | 124 ++++++++++++++++++++++++++++++++++++--------- include/configs/efikamx.h | 4 ++ 2 files changed, 103 insertions(+), 25 deletions(-) V2: Introduce machine_is_efika{mx,sb}() and use where appropriate. The current implementation is temporary. diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c index 5be1f6c..0c4e24b 100644 --- a/board/efikamx/efikamx.c +++ b/board/efikamx/efikamx.c @@ -62,10 +62,13 @@ void efikamx_toggle_led(uint32_t mask); #define EFIKAMX_BOARD_REV_13 0x3 #define EFIKAMX_BOARD_REV_14 0x4 +#define EFIKASB_BOARD_REV_13 0x1 +#define EFIKASB_BOARD_REV_20 0x2 + /* * Board identification */ -u32 get_efika_rev(void) +u32 get_efikamx_rev(void) { u32 rev = 0; /* @@ -97,6 +100,31 @@ u32 get_efika_rev(void) return (~rev & 0x7) + 1; } +inline u32 get_efikasb_rev(void) +{ + u32 rev = 0; + + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0; + + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1; + + return rev; +} + +inline uint32_t get_efika_rev(void) +{ + if (machine_is_efikamx()) + return get_efikamx_rev(); + else + return get_efikasb_rev(); +} + u32 get_board_rev(void) { return get_cpu_rev() | (get_efika_rev() << 8); @@ -268,25 +296,36 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC2_BASE_ADDR, 1}, }; +static inline uint32_t efika_mmc_cd(void) +{ + if (machine_is_efikamx()) + return MX51_PIN_GPIO1_0; + else + return MX51_PIN_EIM_CS2; +} + int board_mmc_getcd(u8 *absent, struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + uint32_t cd = efika_mmc_cd(); if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); + *absent = gpio_get_value(IOMUX_TO_GPIO(cd)); else *absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); return 0; } + int board_mmc_init(bd_t *bis) { int ret; + uint32_t cd = efika_mmc_cd(); /* SDHC1 is used on all revisions, setup control pins first */ - mxc_request_iomux(MX51_PIN_GPIO1_0, + mxc_request_iomux(cd, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_0, + mxc_iomux_set_pad(cd, PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | @@ -298,11 +337,12 @@ int board_mmc_init(bd_t *bis) PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_SRE_FAST); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); + gpio_direction_input(IOMUX_TO_GPIO(cd)); gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */ - if (get_efika_rev() < EFIKAMX_BOARD_REV_12) { + if (machine_is_efikasb() || (machine_is_efikamx() && + (get_efika_rev() < EFIKAMX_BOARD_REV_12))) { /* SDHC1 IOMUX */ mxc_request_iomux(MX51_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); @@ -414,6 +454,7 @@ int board_mmc_init(bd_t *bis) ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); } + return ret; } #endif @@ -493,27 +534,44 @@ static inline void setup_iomux_ata(void) { } */ void setup_iomux_led(void) { - /* Blue LED */ - mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); - - /* Green LED */ - mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0); - - /* Red LED */ - mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0); + if (machine_is_efikamx()) { + /* Blue LED */ + mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); + + /* Green LED */ + mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0); + + /* Red LED */ + mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0); + } else { + /* CAPS-LOCK LED */ + mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0); + + /* ALARM-LED LED */ + mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0); + } } void efikamx_toggle_led(uint32_t mask) { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), - mask & EFIKAMX_LED_BLUE); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), - mask & EFIKAMX_LED_GREEN); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), - mask & EFIKAMX_LED_RED); + if (machine_is_efikamx()) { + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), + mask & EFIKAMX_LED_BLUE); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), + mask & EFIKAMX_LED_GREEN); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), + mask & EFIKAMX_LED_RED); + } else { + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), + mask & EFIKAMX_LED_BLUE); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), + !(mask & EFIKAMX_LED_GREEN)); + } } /* @@ -607,7 +665,6 @@ int board_early_init_f(void) int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_MX51_EFIKAMX; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; return 0; @@ -629,7 +686,24 @@ int board_late_init(void) int checkboard(void) { - puts("Board: Efika MX\n"); + u32 rev = get_efika_rev(); + + if (machine_is_efikamx()) { + printf("Board: Efika MX, rev1.%i\n", rev & 0xf); + return 0; + } else { + switch (rev) { + case EFIKASB_BOARD_REV_13: + printf("Board: Efika SB rev1.3\n"); + break; + case EFIKASB_BOARD_REV_20: + printf("Board: Efika SB rev2.0\n"); + break; + default: + printf("Board: Efika SB, rev Unknown\n"); + break; + } + } return 0; } diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h index fdd0a14..54f48e4 100644 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@ -31,6 +31,10 @@ */ /* An i.MX51 CPU */ #define CONFIG_MX51 + +#define machine_is_efikamx() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKAMX) +#define machine_is_efikasb() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKASB) + #include #define CONFIG_SYS_MX5_HCLK 24000000