From patchwork Sat Sep 24 18:22:48 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 116244 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 77196B6F70 for ; Sun, 25 Sep 2011 04:56:31 +1000 (EST) Received: from localhost ([::1]:51101 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R7Wsv-0005ln-Ae for incoming@patchwork.ozlabs.org; Sat, 24 Sep 2011 14:23:33 -0400 Received: from eggs.gnu.org ([140.186.70.92]:47064) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R7Wsb-00052d-0i for qemu-devel@nongnu.org; Sat, 24 Sep 2011 14:23:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R7WsW-0003ju-Iw for qemu-devel@nongnu.org; Sat, 24 Sep 2011 14:23:12 -0400 Received: from mail-qy0-f173.google.com ([209.85.216.173]:47497) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R7WsW-0003KH-En for qemu-devel@nongnu.org; Sat, 24 Sep 2011 14:23:08 -0400 Received: by mail-qy0-f173.google.com with SMTP id 1so7609784qyc.4 for ; Sat, 24 Sep 2011 11:23:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:from:date:message-id:subject:to:content-type; bh=+da78KiRPXwocLBZ7Y46gt2QQ/jGRAI4Ec5UMYZ/0gE=; b=HCM3Cj2ZK0D0TlIceodTVt2SgBtDFhJRSu298c3SZRZRVw1gTsixliexybrJR/LWUy xxkbISB80ishTqCk87AVqLcoTmaqM711XakI4P6J4WTAeQ/ZytdLthjh7rKpQltwnLZJ +mdQWvfoqlP/NwPdzns9EmoIXlc4r6xIFJDjw= Received: by 10.224.195.8 with SMTP id ea8mr3910229qab.159.1316888588210; Sat, 24 Sep 2011 11:23:08 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.6.129 with HTTP; Sat, 24 Sep 2011 11:22:48 -0700 (PDT) From: Blue Swirl Date: Sat, 24 Sep 2011 18:22:48 +0000 Message-ID: To: qemu-devel X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.216.173 Subject: [Qemu-devel] [PATCH 19/26] Sparc: convert mmu_helper to trace framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Blue Swirl --- target-sparc/mmu_helper.c | 64 ++++++++++++++------------------------------- trace-events | 10 +++++++ 2 files changed, 30 insertions(+), 44 deletions(-) %"PRIx64" context %"PRIx64 +mmu_helper_tmiss(uint64_t address, uint64_t context) "TMISS at %"PRIx64" context %"PRIx64 +mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64 +mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=%"PRIx64" secondary context=%"PRIx64" address=%"PRIx64 +mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at %"PRIx64" -> %"PRIx64", mmu_idx=%d tl=%d primary context=%"PRIx64" secondary context=%"PRIx64 diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c index 5743081..8cdc224 100644 --- a/target-sparc/mmu_helper.c +++ b/target-sparc/mmu_helper.c @@ -18,15 +18,7 @@ */ #include "cpu.h" - -//#define DEBUG_MMU - -#ifdef DEBUG_MMU -#define DPRINTF_MMU(fmt, ...) \ - do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF_MMU(fmt, ...) do {} while (0) -#endif +#include "trace.h" /* Sparc MMU emulation */ @@ -538,10 +530,7 @@ static int get_physical_address_data(CPUState *env, if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) { do_fault = 1; sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */ - - DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64 - " mmu_idx=%d tl=%d\n", - address, context, mmu_idx, env->tl); + trace_mmu_helper_dfault(address, context, mmu_idx, env->tl); } if (rw == 4) { if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) { @@ -562,9 +551,7 @@ static int get_physical_address_data(CPUState *env, do_fault = 1; env->exception_index = TT_DPROT; - DPRINTF_MMU("DPROT at %" PRIx64 " context %" PRIx64 - " mmu_idx=%d tl=%d\n", - address, context, mmu_idx, env->tl); + trace_mmu_helper_dprot(address, context, mmu_idx, env->tl); } if (!do_fault) { @@ -598,8 +585,7 @@ static int get_physical_address_data(CPUState *env, } } - DPRINTF_MMU("DMISS at %" PRIx64 " context %" PRIx64 "\n", - address, context); + trace_mmu_helper_dmiss(address, context); /* * On MMU misses: @@ -662,8 +648,7 @@ static int get_physical_address_code(CPUState *env, env->immu.tag_access = (address & ~0x1fffULL) | context; - DPRINTF_MMU("TFAULT at %" PRIx64 " context %" PRIx64 "\n", - address, context); + trace_mmu_helper_tfault(address, context); return 1; } @@ -673,8 +658,7 @@ static int get_physical_address_code(CPUState *env, } } - DPRINTF_MMU("TMISS at %" PRIx64 " context %" PRIx64 "\n", - address, context); + trace_mmu_helper_tmiss(address, context); /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */ env->immu.tag_access = (address & ~0x1fffULL) | context; @@ -691,21 +675,20 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical, everything when an entry is evicted. */ *page_size = TARGET_PAGE_SIZE; -#if defined(DEBUG_MMU) /* safety net to catch wrong softmmu index use from dynamic code */ if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) { - DPRINTF_MMU("get_physical_address %s tl=%d mmu_idx=%d" - " primary context=%" PRIx64 - " secondary context=%" PRIx64 - " address=%" PRIx64 - "\n", - (rw == 2 ? "CODE" : "DATA"), - env->tl, mmu_idx, - env->dmmu.mmu_primary_context, - env->dmmu.mmu_secondary_context, - address); + if (rw == 2) { + trace_mmu_helper_get_phys_addr_code(env->tl, mmu_idx, + env->dmmu.mmu_primary_context, + env->dmmu.mmu_secondary_context, + address); + } else { + trace_mmu_helper_get_phys_addr_data(env->tl, mmu_idx, + env->dmmu.mmu_primary_context, + env->dmmu.mmu_secondary_context, + address); + } } -#endif if (rw == 2) { return get_physical_address_code(env, physical, prot, address, @@ -732,16 +715,9 @@ int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1)); - DPRINTF_MMU("Translate at %" PRIx64 " -> %" PRIx64 "," - " vaddr %" PRIx64 - " mmu_idx=%d" - " tl=%d" - " primary context=%" PRIx64 - " secondary context=%" PRIx64 - "\n", - address, paddr, vaddr, mmu_idx, env->tl, - env->dmmu.mmu_primary_context, - env->dmmu.mmu_secondary_context); + trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl, + env->dmmu.mmu_primary_context, + env->dmmu.mmu_secondary_context); tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size); return 0; diff --git a/trace-events b/trace-events index a31d9aa..718e0d5 100644 --- a/trace-events +++ b/trace-events @@ -502,3 +502,13 @@ escc_sunkbd_event_in(int ch) "Untranslated keycode %2.2x" escc_sunkbd_event_out(int ch) "Translated keycode %2.2x" escc_kbd_command(int val) "Command %d" escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=%01x" + +# target-sparc/mmu_helper.c +mmu_helper_dfault(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DFAULT at %"PRIx64" context %"PRIx64" mmu_idx=%d tl=%d" +mmu_helper_dprot(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DPROT at %"PRIx64" context %"PRIx64" mmu_idx=%d tl=%d" +mmu_helper_dmiss(uint64_t address, uint64_t context) "DMISS at %"PRIx64" context %"PRIx64 +mmu_helper_tfault(uint64_t address, uint64_t context) "TFAULT at