From patchwork Fri Sep 13 11:53:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 1162047 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46VDYM0JTyz9sCJ for ; Fri, 13 Sep 2019 21:53:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729461AbfIMLx0 (ORCPT ); Fri, 13 Sep 2019 07:53:26 -0400 Received: from foss.arm.com ([217.140.110.172]:42120 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727540AbfIMLx0 (ORCPT ); Fri, 13 Sep 2019 07:53:26 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C50D228; Fri, 13 Sep 2019 04:53:25 -0700 (PDT) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 70F253F71F; Fri, 13 Sep 2019 04:53:23 -0700 (PDT) From: Andrew Murray To: Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Rob Herring , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, Mike Leach , Sudeep Holla , Al.Grant@arm.com, Leo Yan , devicetree@vger.kernel.org, coresight@lists.linaro.org Subject: [PATCH v6 2/3] dt-bindings: arm: coresight: Add support for coresight-loses-context-with-cpu Date: Fri, 13 Sep 2019 12:53:11 +0100 Message-Id: <20190913115312.12943-3-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190913115312.12943-1-andrew.murray@arm.com> References: <20190913115312.12943-1-andrew.murray@arm.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some coresight components, because of choices made during hardware integration, require their state to be saved and restored across CPU low power states. The software has no reliable method of detecting when save/restore is required thus let's add a binding to inform the kernel. Signed-off-by: Andrew Murray Reviewed-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/coresight.txt | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index fcc3bacfd8bc..d02c42d21f2f 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -87,6 +87,15 @@ its hardware characteristcs. * port or ports: see "Graph bindings for Coresight" below. +* Optional properties for all components: + + * arm,coresight-loses-context-with-cpu : boolean. Indicates that the + hardware will lose register context on CPU power down (e.g. CPUIdle). + An example of where this may be needed are systems which contain a + coresight component and CPU in the same power domain. When the CPU + powers down the coresight component also powers down and loses its + context. This property is currently only used for the ETM 4.x driver. + * Optional properties for ETM/PTMs: * arm,cp14: must be present if the system accesses ETM/PTM management