From patchwork Fri Sep 13 06:07:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 1161849 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Xu7qGyyT"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46V4wg27mJz9s4Y for ; Fri, 13 Sep 2019 16:09:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728404AbfIMGJ3 (ORCPT ); Fri, 13 Sep 2019 02:09:29 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9593 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728385AbfIMGJ2 (ORCPT ); Fri, 13 Sep 2019 02:09:28 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 12 Sep 2019 23:09:29 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 12 Sep 2019 23:09:28 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 12 Sep 2019 23:09:28 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 13 Sep 2019 06:09:28 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 13 Sep 2019 06:09:28 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.65.118]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 12 Sep 2019 23:09:27 -0700 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V9 8/8] arm64: defconfig: Enable tegra XUDC support Date: Fri, 13 Sep 2019 11:37:53 +0530 Message-ID: <1568354873-24073-9-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568354873-24073-1-git-send-email-nkristam@nvidia.com> References: <1568354873-24073-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1568354970; bh=1fQ3YD6tFlPCpxU+owhmaKVvKAG0D39iX9cspX2QD3w=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Xu7qGyyTZVLPsXkXg7VdN3RYRGNjh91iDE41GLrulfKpAjtayUMX4TDhYUcE7bVNJ 5aYEDTNTLGNtkgNM7k6BYUpkDyeIE3/94b1GUiwRsjIITrtAuMAkAxnpzZZ4e7Fz4k sbWfBQjhJ1adTC7/rdIcVOP7pMhPzTzfienLIHvFKsMRwGHl5gnrAPU6qUGCwB+kPd joHv05v3aGReE/VTeXY8L6jJFckZJMPhRzmbT6rnS+gdt3Xed5APIpH+L3xuxwWDBb a6Vnz7zeEsAykoOv8ZhEYJZNWO30U0T4a/4yC1YO8u3wLXO2kdChLnPCz9Nr27HMjr wKjnx2nQTO4Ow== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable Nvidia XUSB device mode controller driver and USB GPIO Based Connection Detection Driver as module. Signed-off-by: Nagarjuna Kristam --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 358b163..de2826c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -575,6 +575,7 @@ CONFIG_SND_SIMPLE_CARD=m CONFIG_SND_AUDIO_GRAPH_CARD=m CONFIG_I2C_HID=m CONFIG_USB=y +CONFIG_USB_CONN_GPIO=m CONFIG_USB_OTG=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_TEGRA=y @@ -600,6 +601,7 @@ CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y CONFIG_USB_RENESAS_USBHS_UDC=m CONFIG_USB_RENESAS_USB3=m +CONFIG_USB_TEGRA_XUDC=m CONFIG_TYPEC=m CONFIG_TYPEC_HD3SS3220=m CONFIG_MMC=y