From patchwork Fri Sep 13 06:07:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 1161848 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="SoDe+ASD"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46V4wV1zzcz9s4Y for ; Fri, 13 Sep 2019 16:09:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727487AbfIMGJT (ORCPT ); Fri, 13 Sep 2019 02:09:19 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:19208 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725775AbfIMGJS (ORCPT ); Fri, 13 Sep 2019 02:09:18 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 12 Sep 2019 23:09:22 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 12 Sep 2019 23:09:17 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 12 Sep 2019 23:09:17 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 13 Sep 2019 06:09:17 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 13 Sep 2019 06:09:17 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.65.118]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 12 Sep 2019 23:09:16 -0700 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V9 5/8] arm64: tegra: Add xudc node for Tegra210 Date: Fri, 13 Sep 2019 11:37:50 +0530 Message-ID: <1568354873-24073-6-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568354873-24073-1-git-send-email-nkristam@nvidia.com> References: <1568354873-24073-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1568354962; bh=q0M5Gc1mkimDBK7Ykg1QnyBRB1lOKTLjMP2xt1WkSuw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=SoDe+ASDZcZCLl5KyXGb3fkP5l3b3iMQYFWH/G9PL5z1iAW8/I1X+lZPOJHWsP5V/ tmww12to1Rys42Wf53q42baXPSJ8BUFEN1whkCkBN9wqaEbEaLoA8F3XISZiOJ+5Qw hsIDtXQZRPsMgpI5+uw1fF+PFTYZfHn52CwVHzA4D7/1mwsI3ATvKznXvzh/crBz2h s1G7y9y5mFr5Bw5zvQ7c+L8ItqbmVNDTqvh+qztixDwpDf6bwZtsb9buMookh6rLK5 cVj4FnSi1VxB2pw+jnbMkcLjePKsZmlxj/MPdQCjdg6bCdohIX9x0UXiJDwPg71Pms tzdsLz1Rm3Njg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra210 has one XUSB device mode controller, which can be operated HS and SS modes. Add DT support for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam Reviewed-by: JC Kuo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 6597531..5de0b36 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1203,6 +1203,25 @@ status = "disabled"; }; + usb@700d0000 { + compatible = "nvidia,tegra210-xudc"; + reg = <0x0 0x700d0000 0x0 0x8000>, + <0x0 0x700d8000 0x0 0x1000>, + <0x0 0x700d9000 0x0 0x1000>; + reg-names = "base", "fpci", "ipfs"; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, + <&tegra_car TEGRA210_CLK_XUSB_SS>, + <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>; + clock-names = "dev", "ss", "ss_src", "hs_src", "fs_src"; + power-domains = <&pd_xusbdev>, <&pd_xusbss>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&padctl>; + status = "disabled"; + }; + mipi: mipi@700e3000 { compatible = "nvidia,tegra210-mipi"; reg = <0x0 0x700e3000 0x0 0x100>;