Patchwork [U-Boot,1/2] powerpc/p2041rdb: updated description of cpld command

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Submitter Kumar Gala
Date Sept. 23, 2011, 5:54 p.m.
Message ID <1316800490-16284-1-git-send-email-galak@kernel.crashing.org>
Download mbox | patch
Permalink /patch/116164/
State Accepted
Commit 60820457ccf6e9c8b7a9afc2b45c78a84f8edda8
Headers show

Comments

Kumar Gala - Sept. 23, 2011, 5:54 p.m.
From: Shaohui Xie <Shaohui.Xie@freescale.com>

According to CPLD 2.2, the default configuration is changed, so updated the
description of CPLD command, otherwise it will confusing.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/p2041rdb/cpld.c |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)
Kumar Gala - Oct. 3, 2011, 1:47 p.m.
On Sep 23, 2011, at 12:54 PM, Kumar Gala wrote:

> From: Shaohui Xie <Shaohui.Xie@freescale.com>
> 
> According to CPLD 2.2, the default configuration is changed, so updated the
> description of CPLD command, otherwise it will confusing.
> 
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> board/freescale/p2041rdb/cpld.c |   16 ++++++++--------
> 1 files changed, 8 insertions(+), 8 deletions(-)

applied to 85xx

- k

Patch

diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c
index 37b0ed5..2ad89a8 100644
--- a/board/freescale/p2041rdb/cpld.c
+++ b/board/freescale/p2041rdb/cpld.c
@@ -159,14 +159,14 @@  U_BOOT_CMD(
 	"cpld_cmd watchdog <watchdog_period> - set the watchdog period\n"
 	"	period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n"
 	"cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
-	"	lane 6: 0 -> slot1 (Default)\n"
-	"		1 -> SGMII\n"
-	"	lane a: 0 -> slot2 (Default)\n"
-	"		1 -> AURORA\n"
-	"	lane c: 0 -> slot2 (Default)\n"
-	"		1 -> SATA0\n"
-	"	lane d: 0 -> slot2 (Default)\n"
-	"		1 -> SATA1\n"
+	"	lane 6: 0 -> slot1\n"
+	"		1 -> SGMII (Default)\n"
+	"	lane a: 0 -> slot2\n"
+	"		1 -> AURORA (Default)\n"
+	"	lane c: 0 -> slot2\n"
+	"		1 -> SATA0 (Default)\n"
+	"	lane d: 0 -> slot2\n"
+	"		1 -> SATA1 (Default)\n"
 #ifdef DEBUG
 	"cpld_cmd dump - display the CPLD registers\n"
 #endif