| Message ID | 1568283065-11023-10-git-send-email-ley.foon.tan@intel.com |
|---|---|
| State | Superseded |
| Delegated to: | Simon Goldschmidt |
| Headers | show |
| Series | Add Intel Agilex SoC support | expand |
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan <ley.foon.tan@intel.com> wrote: > > Add clock wrapper functions call to clock DM functions to get clock > frequency and used in cm_print_clock_quick_summary(). > > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> This whole patch looks like a hack to me. However, I was facing the same problem when porting gen5 to DM_CLK (and I haven't found a better way). For now, this is probably OK, but could you find a way to solve this in a cleaner way (without referencing driver includes from arch)? That would be great! Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> > > --- > v4: > - Change to use SYSMGR_SOC64* prefix. > > v3: > - Improved commit message. > - Rename STRATIX10_* to SOCFPGA_SOC64_* > - Include clock_manager_soc64.h and clk-agilex.h. > > v2: > - Get clocks from clock DM. > --- > arch/arm/mach-socfpga/Makefile | 4 + > arch/arm/mach-socfpga/clock_manager_agilex.c | 84 +++++++++++++++++++ > .../mach-socfpga/include/mach/clock_manager.h | 2 + > .../include/mach/clock_manager_agilex.h | 14 ++++ > 4 files changed, 104 insertions(+) > create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c > create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile > index dab34d0ef2..a403b46b47 100644 > --- a/arch/arm/mach-socfpga/Makefile > +++ b/arch/arm/mach-socfpga/Makefile > @@ -39,6 +39,10 @@ obj-y += wrap_pinmux_config_s10.o > obj-y += wrap_pll_config_s10.o > endif > > +ifdef CONFIG_TARGET_SOCFPGA_AGILEX > +obj-y += clock_manager_agilex.o > +endif > + > ifdef CONFIG_SPL_BUILD > ifdef CONFIG_TARGET_SOCFPGA_GEN5 > obj-y += spl_gen5.o > diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c > new file mode 100644 > index 0000000000..9e0b3ef29d > --- /dev/null > +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c > @@ -0,0 +1,84 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2019 Intel Corporation <www.intel.com> > + * > + */ > + > +#include <clk.h> > +#include <common.h> > +#include <dm.h> > +#include <asm/arch/clock_manager.h> > +#include <asm/arch/system_manager.h> > +#include <asm/io.h> > +#include <dt-bindings/clock/socfpga-soc64-clock.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static ulong cm_get_rate_dm(u32 id) > +{ > + struct udevice *dev; > + struct clk clk; > + ulong rate; > + int ret; > + > + ret = uclass_get_device_by_driver(UCLASS_CLK, > + DM_GET_DRIVER(socfpga_agilex_clk), > + &dev); > + if (ret) > + return 0; > + > + clk.id = id; > + ret = clk_request(dev, &clk); > + if (ret < 0) > + return 0; > + > + rate = clk_get_rate(&clk); > + > + clk_free(&clk); > + > + if ((rate == (unsigned long)-ENOSYS) || > + (rate == (unsigned long)-ENXIO) || > + (rate == (unsigned long)-EIO)) { > + debug("%s id %u: clk_get_rate err: %ld\n", > + __func__, id, rate); > + return 0; > + } > + > + return rate; > +} > + > +static u32 cm_get_rate_dm_khz(u32 id) > +{ > + return cm_get_rate_dm(id) / 1000; > +} > + > +unsigned long cm_get_mpu_clk_hz(void) > +{ > + return cm_get_rate_dm(SOCFPGA_SOC64_MPU_CLK); > +} > + > +unsigned int cm_get_l4_sys_free_clk_hz(void) > +{ > + return cm_get_rate_dm(SOCFPGA_SOC64_L4_SYS_FREE_CLK); > +} > + > +u32 cm_get_qspi_controller_clk_hz(void) > +{ > + return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); > +} > + > +void cm_print_clock_quick_summary(void) > +{ > + printf("MPU %10d kHz\n", > + cm_get_rate_dm_khz(SOCFPGA_SOC64_MPU_CLK)); > + printf("L4 Main %8d kHz\n", > + cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_MAIN_CLK)); > + printf("L4 sys free %8d kHz\n", > + cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_SYS_FREE_CLK)); > + printf("L4 MP %8d kHz\n", > + cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_MP_CLK)); > + printf("L4 SP %8d kHz\n", > + cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_SP_CLK)); > + printf("SDMMC %8d kHz\n", > + cm_get_rate_dm_khz(SOCFPGA_SOC64_SDMMC_CLK)); > +} > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h > index 4f9d10dd78..5d3ee2a83f 100644 > --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h > @@ -20,6 +20,8 @@ void cm_print_clock_quick_summary(void); > #include <asm/arch/clock_manager_arria10.h> > #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) > #include <asm/arch/clock_manager_s10.h> > +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) > +#include <asm/arch/clock_manager_agilex.h> > #endif > > #endif /* _CLOCK_MANAGER_H_ */ > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h > new file mode 100644 > index 0000000000..386e82a4e3 > --- /dev/null > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h > @@ -0,0 +1,14 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2019 Intel Corporation <www.intel.com> > + */ > + > +#ifndef _CLOCK_MANAGER_AGILEX_ > +#define _CLOCK_MANAGER_AGILEX_ > + > +unsigned long cm_get_mpu_clk_hz(void); > + > +#include <asm/arch/clock_manager_soc64.h> > +#include "../../../../../drivers/clk/altera/clk-agilex.h" > + > +#endif /* _CLOCK_MANAGER_AGILEX_ */ > -- > 2.19.0 >
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index dab34d0ef2..a403b46b47 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -39,6 +39,10 @@ obj-y += wrap_pinmux_config_s10.o obj-y += wrap_pll_config_s10.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX +obj-y += clock_manager_agilex.o +endif + ifdef CONFIG_SPL_BUILD ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += spl_gen5.o diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c new file mode 100644 index 0000000000..9e0b3ef29d --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/io.h> +#include <dt-bindings/clock/socfpga-soc64-clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +static ulong cm_get_rate_dm(u32 id) +{ + struct udevice *dev; + struct clk clk; + ulong rate; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(socfpga_agilex_clk), + &dev); + if (ret) + return 0; + + clk.id = id; + ret = clk_request(dev, &clk); + if (ret < 0) + return 0; + + rate = clk_get_rate(&clk); + + clk_free(&clk); + + if ((rate == (unsigned long)-ENOSYS) || + (rate == (unsigned long)-ENXIO) || + (rate == (unsigned long)-EIO)) { + debug("%s id %u: clk_get_rate err: %ld\n", + __func__, id, rate); + return 0; + } + + return rate; +} + +static u32 cm_get_rate_dm_khz(u32 id) +{ + return cm_get_rate_dm(id) / 1000; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + return cm_get_rate_dm(SOCFPGA_SOC64_MPU_CLK); +} + +unsigned int cm_get_l4_sys_free_clk_hz(void) +{ + return cm_get_rate_dm(SOCFPGA_SOC64_L4_SYS_FREE_CLK); +} + +u32 cm_get_qspi_controller_clk_hz(void) +{ + return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %10d kHz\n", + cm_get_rate_dm_khz(SOCFPGA_SOC64_MPU_CLK)); + printf("L4 Main %8d kHz\n", + cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_MAIN_CLK)); + printf("L4 sys free %8d kHz\n", + cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_SYS_FREE_CLK)); + printf("L4 MP %8d kHz\n", + cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_MP_CLK)); + printf("L4 SP %8d kHz\n", + cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_SP_CLK)); + printf("SDMMC %8d kHz\n", + cm_get_rate_dm_khz(SOCFPGA_SOC64_SDMMC_CLK)); +} diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 4f9d10dd78..5d3ee2a83f 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -20,6 +20,8 @@ void cm_print_clock_quick_summary(void); #include <asm/arch/clock_manager_arria10.h> #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/clock_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/clock_manager_agilex.h> #endif #endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h new file mode 100644 index 0000000000..386e82a4e3 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#ifndef _CLOCK_MANAGER_AGILEX_ +#define _CLOCK_MANAGER_AGILEX_ + +unsigned long cm_get_mpu_clk_hz(void); + +#include <asm/arch/clock_manager_soc64.h> +#include "../../../../../drivers/clk/altera/clk-agilex.h" + +#endif /* _CLOCK_MANAGER_AGILEX_ */
Add clock wrapper functions call to clock DM functions to get clock frequency and used in cm_print_clock_quick_summary(). Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> --- v4: - Change to use SYSMGR_SOC64* prefix. v3: - Improved commit message. - Rename STRATIX10_* to SOCFPGA_SOC64_* - Include clock_manager_soc64.h and clk-agilex.h. v2: - Get clocks from clock DM. --- arch/arm/mach-socfpga/Makefile | 4 + arch/arm/mach-socfpga/clock_manager_agilex.c | 84 +++++++++++++++++++ .../mach-socfpga/include/mach/clock_manager.h | 2 + .../include/mach/clock_manager_agilex.h | 14 ++++ 4 files changed, 104 insertions(+) create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h