diff mbox series

[U-Boot,2/4] arm: mxs: fix comments in arch_cpu_init to match the code

Message ID 20190912091656.14301-3-rasmus.villemoes@prevas.dk
State Accepted
Commit fb9462522991a50b95ea00fdbc495634bb6a7cca
Delegated to: Stefano Babic
Headers show
Series arm: mxs: mxs_set_gpmiclk | expand

Commit Message

Rasmus Villemoes Sept. 12, 2019, 9:17 a.m. UTC 
The comment says to clear the bypass bit, but in fact it sets it, thus
selecting ref_xtal. And the next line of code does not set the divider
to 12, but to (the reset value of) 1.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
---
 arch/arm/cpu/arm926ejs/mxs/mxs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 85c65dcb44..585c53baf6 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -98,11 +98,11 @@  int arch_cpu_init(void)
 	/*
 	 * Enable NAND clock
 	 */
-	/* Clear bypass bit */
+	/* Set bypass bit */
 	writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
 		&clkctrl_regs->hw_clkctrl_clkseq_set);
 
-	/* Set GPMI clock to ref_gpmi / 12 */
+	/* Set GPMI clock to ref_xtal / 1 */
 	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
 		CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);