[U-Boot,2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*
diff mbox series

Message ID 20190910170621.2064-2-vigneshr@ti.com
State New
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series
  • [U-Boot,1/2] spi-nor: spi-nor-ids: Merge "n25q512a" and "mt25qu512a" entries
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Commit Message

Vignesh Raghavendra Sept. 10, 2019, 5:06 p.m. UTC
Not all variants of n25q256* and n25q512* support 4 Byte stateless
addressing opcodes and there is no easy way to discover at runtime
whether the flash supports this feature or not.
Therefore don't set SPI_NOR_4B_OPCODES for these flashes.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
For n25q512ax3:
Tested-by: Eugeniy Paltsev <paltsev@synopsys.com>
---
 drivers/mtd/spi/spi-nor-ids.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Simon Goldschmidt Sept. 10, 2019, 7:18 p.m. UTC | #1
Vignesh Raghavendra <vigneshr@ti.com> schrieb am Di., 10. Sep. 2019, 19:07:

> Not all variants of n25q256* and n25q512* support 4 Byte stateless
> addressing opcodes and there is no easy way to discover at runtime
> whether the flash supports this feature or not.
> Therefore don't set SPI_NOR_4B_OPCODES for these flashes.
>

I have one of those that supports 4 Byte opposes and would be glad if I
could use them. Is there any chance of flagging the devicetree or something
that enables them?

Regards,
Simon


> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
> For n25q512ax3:
> Tested-by: Eugeniy Paltsev <paltsev@synopsys.com>
> ---
>  drivers/mtd/spi/spi-nor-ids.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index f32a6c7d464b..5a7fe07c8309 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -161,10 +161,10 @@ const struct flash_info spi_nor_ids[] = {
>         { INFO("n25q064a",    0x20bb17, 0, 64 * 1024,  128, SECT_4K |
> SPI_NOR_QUAD_READ) },
>         { INFO("n25q128a11",  0x20bb18, 0, 64 * 1024,  256, SECT_4K |
> SPI_NOR_QUAD_READ) },
>         { INFO("n25q128a13",  0x20ba18, 0, 64 * 1024,  256, SECT_4K |
> SPI_NOR_QUAD_READ) },
> -       { INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> -       { INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024, 1024,
> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> -       { INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024, 1024,
> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> +       { INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ) },
>         { INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>         { INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>         { INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> --
> 2.23.0
>
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
>
Ashish Kumar Sept. 11, 2019, 8:49 a.m. UTC | #2
> -----Original Message-----
> From: Vignesh Raghavendra <vigneshr@ti.com>
> Sent: Tuesday, September 10, 2019 10:36 PM
> To: Jagan Teki <jagan@openedev.com>
> Cc: Vignesh Raghavendra <vigneshr@ti.com>; u-boot@lists.denx.de; Tom
> Rini <trini@konsulko.com>; Eugeniy Paltsev
> <Eugeniy.Paltsev@synopsys.com>; Alexey.Brodkin@synopsys.com; Ashish
> Kumar <ashish.kumar@nxp.com>
> Subject: [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable
> SPI_NOR_4B_OPCODES for n25q512* and n25q256*
> 
> Caution: EXT Email
> 
> Not all variants of n25q256* and n25q512* support 4 Byte stateless
> addressing opcodes and there is no easy way to discover at runtime whether
> the flash supports this feature or not.
> Therefore don't set SPI_NOR_4B_OPCODES for these flashes.
Hi Vignesh, 

I think it will be good to keep it here and disable this for boards by using not set flag in config
Like
# SPI_NOR_4B_OPCODES is not set

Regards
Ashish 
> 
> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> For n25q512ax3:
> Tested-by: Eugeniy Paltsev <paltsev@synopsys.com>
> ---
>  drivers/mtd/spi/spi-nor-ids.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index f32a6c7d464b..5a7fe07c8309 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -161,10 +161,10 @@ const struct flash_info spi_nor_ids[] = {
>         { INFO("n25q064a",    0x20bb17, 0, 64 * 1024,  128, SECT_4K |
> SPI_NOR_QUAD_READ) },
>         { INFO("n25q128a11",  0x20bb18, 0, 64 * 1024,  256, SECT_4K |
> SPI_NOR_QUAD_READ) },
>         { INFO("n25q128a13",  0x20ba18, 0, 64 * 1024,  256, SECT_4K |
> SPI_NOR_QUAD_READ) },
> -       { INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> -       { INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024, 1024,
> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> -       { INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024, 1024,
> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> +       { INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
> + USE_FSR | SPI_NOR_QUAD_READ) },
>         { INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>         { INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>         { INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> --
> 2.23.0
Simon Goldschmidt Sept. 11, 2019, 9:41 a.m. UTC | #3
Ashish Kumar <ashish.kumar@nxp.com> schrieb am Mi., 11. Sep. 2019, 10:49:

>
>
> > -----Original Message-----
> > From: Vignesh Raghavendra <vigneshr@ti.com>
> > Sent: Tuesday, September 10, 2019 10:36 PM
> > To: Jagan Teki <jagan@openedev.com>
> > Cc: Vignesh Raghavendra <vigneshr@ti.com>; u-boot@lists.denx.de; Tom
> > Rini <trini@konsulko.com>; Eugeniy Paltsev
> > <Eugeniy.Paltsev@synopsys.com>; Alexey.Brodkin@synopsys.com; Ashish
> > Kumar <ashish.kumar@nxp.com>
> > Subject: [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable
> > SPI_NOR_4B_OPCODES for n25q512* and n25q256*
> >
> > Caution: EXT Email
> >
> > Not all variants of n25q256* and n25q512* support 4 Byte stateless
> > addressing opcodes and there is no easy way to discover at runtime
> whether
> > the flash supports this feature or not.
> > Therefore don't set SPI_NOR_4B_OPCODES for these flashes.
> Hi Vignesh,
>
> I think it will be good to keep it here and disable this for boards by
> using not set flag in config
> Like
> # SPI_NOR_4B_OPCODES is not set
>

I'd prefer to take this patch, as this is what Linux does. I think it's
better to have an opt-in option. That way, all chips work with the default
settings (even if that means some chips don't use 4 baste opcodes even if
they could).

Still, so we have such an op-in possibility to enable 4 byte opcodes on
these chips?

Regards,
Simon


> Regards
> Ashish
> >
> > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> For n25q512ax3:
> > Tested-by: Eugeniy Paltsev <paltsev@synopsys.com>
> > ---
> >  drivers/mtd/spi/spi-nor-ids.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-ids.c
> b/drivers/mtd/spi/spi-nor-ids.c
> > index f32a6c7d464b..5a7fe07c8309 100644
> > --- a/drivers/mtd/spi/spi-nor-ids.c
> > +++ b/drivers/mtd/spi/spi-nor-ids.c
> > @@ -161,10 +161,10 @@ const struct flash_info spi_nor_ids[] = {
> >         { INFO("n25q064a",    0x20bb17, 0, 64 * 1024,  128, SECT_4K |
> > SPI_NOR_QUAD_READ) },
> >         { INFO("n25q128a11",  0x20bb18, 0, 64 * 1024,  256, SECT_4K |
> > SPI_NOR_QUAD_READ) },
> >         { INFO("n25q128a13",  0x20ba18, 0, 64 * 1024,  256, SECT_4K |
> > SPI_NOR_QUAD_READ) },
> > -       { INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K |
> > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K |
> > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> >         { INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K |
> > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> > -       { INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024, 1024,
> > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> > -       { INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
> USE_FSR |
> > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024, 1024,
> > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> > +       { INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
> > + USE_FSR | SPI_NOR_QUAD_READ) },
> >         { INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048, SECT_4K |
> USE_FSR |
> > SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >         { INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048, SECT_4K |
> USE_FSR |
> > SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >         { INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096, SECT_4K |
> USE_FSR |
> > SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> > --
> > 2.23.0
>
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot
>
Vignesh Raghavendra Sept. 11, 2019, 10:07 a.m. UTC | #4
Hi Ashish, Simon,

On 11/09/19 3:11 PM, Simon Goldschmidt wrote:
> 
> 
> Ashish Kumar <ashish.kumar@nxp.com <mailto:ashish.kumar@nxp.com>>
> schrieb am Mi., 11. Sep. 2019, 10:49:
> 
> 
> 
>     > -----Original Message-----
>     > From: Vignesh Raghavendra <vigneshr@ti.com <mailto:vigneshr@ti.com>>
>     > Sent: Tuesday, September 10, 2019 10:36 PM
>     > To: Jagan Teki <jagan@openedev.com <mailto:jagan@openedev.com>>
>     > Cc: Vignesh Raghavendra <vigneshr@ti.com
>     <mailto:vigneshr@ti.com>>; u-boot@lists.denx.de
>     <mailto:u-boot@lists.denx.de>; Tom
>     > Rini <trini@konsulko.com <mailto:trini@konsulko.com>>; Eugeniy Paltsev
>     > <Eugeniy.Paltsev@synopsys.com
>     <mailto:Eugeniy.Paltsev@synopsys.com>>; Alexey.Brodkin@synopsys.com
>     <mailto:Alexey.Brodkin@synopsys.com>; Ashish
>     > Kumar <ashish.kumar@nxp.com <mailto:ashish.kumar@nxp.com>>
>     > Subject: [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable
>     > SPI_NOR_4B_OPCODES for n25q512* and n25q256*
>     >
>     > Caution: EXT Email
>     >
>     > Not all variants of n25q256* and n25q512* support 4 Byte stateless
>     > addressing opcodes and there is no easy way to discover at runtime
>     whether
>     > the flash supports this feature or not.
>     > Therefore don't set SPI_NOR_4B_OPCODES for these flashes.
>     Hi Vignesh,
> 
>     I think it will be good to keep it here and disable this for boards
>     by using not set flag in config
>     Like
>     # SPI_NOR_4B_OPCODES is not set
> 

SPI_NOR_4B_OPCODES is not a config option. Are you suggesting to add
one? config options don't scale well especially when same defconfig is
used for multiple boards that potentially have different flashes

> 
> I'd prefer to take this patch, as this is what Linux does. 

No, this is not what Linux does. There is no opt-in or opt-out option.
Decision to use 4 byte opcode is done at runtime based on flash that's
detected. Either based on info->flags for that part or by parsing SFDP
table. There is no config option of DT option to force 4 byte addressing

> I think it's better to have an opt-in option. That way, all chips work with the
> default settings (even if that means some chips don't use 4 baste
> opcodes even if they could).
> 

One solution would be to look at SFDP tables of two variants of flash
and see if there are any differences that can be used as a clue.

Simon,
Could you provide dump of SFDP tables and all the 6 bytes READ ID of the
flash that you have?

I have asked Eugeniy to provide dumps from his flash on the other
thread. Lets see if something stands out.

Regards
Vignesh

> Still, so we have such an op-in possibility to enable 4 byte opcodes on
> these chips?
> 
> Regards,
> Simon
> 
> 
>     Regards
>     Ashish
>     >
>     > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com
>     <mailto:vigneshr@ti.com>> For n25q512ax3:
>     > Tested-by: Eugeniy Paltsev <paltsev@synopsys.com
>     <mailto:paltsev@synopsys.com>>
>     > ---
>     >  drivers/mtd/spi/spi-nor-ids.c | 6 +++---
>     >  1 file changed, 3 insertions(+), 3 deletions(-)
>     >
>     > diff --git a/drivers/mtd/spi/spi-nor-ids.c
>     b/drivers/mtd/spi/spi-nor-ids.c
>     > index f32a6c7d464b..5a7fe07c8309 100644
>     > --- a/drivers/mtd/spi/spi-nor-ids.c
>     > +++ b/drivers/mtd/spi/spi-nor-ids.c
>     > @@ -161,10 +161,10 @@ const struct flash_info spi_nor_ids[] = {
>     >         { INFO("n25q064a",    0x20bb17, 0, 64 * 1024,  128, SECT_4K |
>     > SPI_NOR_QUAD_READ) },
>     >         { INFO("n25q128a11",  0x20bb18, 0, 64 * 1024,  256, SECT_4K |
>     > SPI_NOR_QUAD_READ) },
>     >         { INFO("n25q128a13",  0x20ba18, 0, 64 * 1024,  256, SECT_4K |
>     > SPI_NOR_QUAD_READ) },
>     > -       { INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K |
>     > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>     > +       { INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K |
>     > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>     >         { INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K |
>     > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>     > -       { INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024,
>     1024,
>     > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>     > -       { INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024,
>     SECT_4K | USE_FSR |
>     > SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>     > +       { INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024,
>     1024,
>     > SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>     > +       { INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
>     > + USE_FSR | SPI_NOR_QUAD_READ) },
>     >         { INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048,
>     SECT_4K | USE_FSR |
>     > SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>     >         { INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048,
>     SECT_4K | USE_FSR |
>     > SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>     >         { INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096,
>     SECT_4K | USE_FSR |
>     > SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>     > --
>     > 2.23.0
> 
>     _______________________________________________
>     U-Boot mailing list
>     U-Boot@lists.denx.de <mailto:U-Boot@lists.denx.de>
>     https://lists.denx.de/listinfo/u-boot
>

Patch
diff mbox series

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index f32a6c7d464b..5a7fe07c8309 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -161,10 +161,10 @@  const struct flash_info spi_nor_ids[] = {
 	{ INFO("n25q064a",    0x20bb17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ INFO("n25q128a11",  0x20bb18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ INFO("n25q128a13",  0x20ba18, 0, 64 * 1024,  256, SECT_4K | SPI_NOR_QUAD_READ) },
-	{ INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-	{ INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
-	{ INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mt25qu512a (n25q512a)",    0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+	{ INFO("n25q512ax3",  0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
 	{ INFO("n25q00",      0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },