[6/9] Remove AND_COMPL_HARD_REG_SET
diff mbox series

Message ID mpt4l1l8nnj.fsf@arm.com
State New
Headers show
Series
  • Make HARD_REG_SETs easier to use
Related show

Commit Message

Richard Sandiford Sept. 9, 2019, 4:01 p.m. UTC
Use "x &= ~y" instead of "AND_COMPL_HARD_REG_SET (x, y)", or just
"x & ~y" if the result is a temporary.  This means that we're splitting
it into two operations, but the compiler should be able to combine them
for reasonable values of FIRST_PSEUDO_REGISTER.


2019-09-09  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* hard-reg-set.h (AND_COMPL_HARD_REG_SET): Delete.
	* caller-save.c (setup_save_areas): Use "&~" instead of
	AND_COMPL_HARD_REG_SET.
	(save_call_clobbered_regs): Likewise.
	* config/epiphany/epiphany.c (epiphany_conditional_register_usage):
	Likewise.
	* config/frv/frv.c (frv_ifcvt_modify_tests): Likewise.
	* config/gcn/gcn.c (gcn_md_reorg): Likewise.
	* config/i386/i386.c (ix86_conditional_register_usage): Likewise.
	* config/mips/mips.c (mips_class_max_nregs): Likewise.
	(mips_conditional_register_usage): Likewise.
	* config/sh/sh.c (output_stack_adjust): Likewise.
	* ira-color.c (form_allocno_hard_regs_nodes_forest): Likewise.
	(setup_profitable_hard_regs): Likewise.
	(get_conflict_and_start_profitable_regs): Likewise.
	* ira-conflicts.c (print_allocno_conflicts): Likewise.
	(ira_build_conflicts): Likewise.
	* ira-costs.c (restrict_cost_classes): Likewise.
	(setup_regno_cost_classes_by_aclass): Likewise.
	* ira-lives.c (process_bb_node_lives): Likewise.
	* ira.c (setup_class_hard_regs, setup_reg_subclasses): Likewise.
	(setup_class_subset_and_memory_move_costs, setup_pressure_classes)
	(setup_allocno_and_important_classes, setup_class_translate_array)
	(setup_reg_class_relations, setup_prohibited_class_mode_regs):
	Likewise.
	* lra-assigns.c (find_hard_regno_for_1): Likewise.
	* lra-constraints.c (prohibited_class_reg_set_mode_p): Likewise.
	(process_alt_operands, inherit_in_ebb): Likewise.
	* lra-eliminations.c (update_reg_eliminate): Likewise.
	* lra-lives.c (process_bb_lives): Likewise.
	* reload1.c (update_eliminables_and_spill, reload_as_needed): Likewise.
	* resource.c (find_dead_or_set_registers): Likewise.
	(mark_target_live_regs): Likewise.
	* sched-deps.c (get_implicit_reg_pending_clobbers): Likewise.
	* sel-sched.c (mark_unavailable_hard_regs): Likewise.
	(implicit_clobber_conflict_p): Likewise.
	* shrink-wrap.c (requires_stack_frame_p): Likewise.
	(try_shrink_wrapping): Likewise.

Comments

Jeff Law Sept. 9, 2019, 5:40 p.m. UTC | #1
On 9/9/19 10:01 AM, Richard Sandiford wrote:
> Use "x &= ~y" instead of "AND_COMPL_HARD_REG_SET (x, y)", or just
> "x & ~y" if the result is a temporary.  This means that we're splitting
> it into two operations, but the compiler should be able to combine them
> for reasonable values of FIRST_PSEUDO_REGISTER.
> 
> 
> 2019-09-09  Richard Sandiford  <richard.sandiford@arm.com>
> 
> gcc/
> 	* hard-reg-set.h (AND_COMPL_HARD_REG_SET): Delete.
> 	* caller-save.c (setup_save_areas): Use "&~" instead of
> 	AND_COMPL_HARD_REG_SET.
> 	(save_call_clobbered_regs): Likewise.
> 	* config/epiphany/epiphany.c (epiphany_conditional_register_usage):
> 	Likewise.
> 	* config/frv/frv.c (frv_ifcvt_modify_tests): Likewise.
> 	* config/gcn/gcn.c (gcn_md_reorg): Likewise.
> 	* config/i386/i386.c (ix86_conditional_register_usage): Likewise.
> 	* config/mips/mips.c (mips_class_max_nregs): Likewise.
> 	(mips_conditional_register_usage): Likewise.
> 	* config/sh/sh.c (output_stack_adjust): Likewise.
> 	* ira-color.c (form_allocno_hard_regs_nodes_forest): Likewise.
> 	(setup_profitable_hard_regs): Likewise.
> 	(get_conflict_and_start_profitable_regs): Likewise.
> 	* ira-conflicts.c (print_allocno_conflicts): Likewise.
> 	(ira_build_conflicts): Likewise.
> 	* ira-costs.c (restrict_cost_classes): Likewise.
> 	(setup_regno_cost_classes_by_aclass): Likewise.
> 	* ira-lives.c (process_bb_node_lives): Likewise.
> 	* ira.c (setup_class_hard_regs, setup_reg_subclasses): Likewise.
> 	(setup_class_subset_and_memory_move_costs, setup_pressure_classes)
> 	(setup_allocno_and_important_classes, setup_class_translate_array)
> 	(setup_reg_class_relations, setup_prohibited_class_mode_regs):
> 	Likewise.
> 	* lra-assigns.c (find_hard_regno_for_1): Likewise.
> 	* lra-constraints.c (prohibited_class_reg_set_mode_p): Likewise.
> 	(process_alt_operands, inherit_in_ebb): Likewise.
> 	* lra-eliminations.c (update_reg_eliminate): Likewise.
> 	* lra-lives.c (process_bb_lives): Likewise.
> 	* reload1.c (update_eliminables_and_spill, reload_as_needed): Likewise.
> 	* resource.c (find_dead_or_set_registers): Likewise.
> 	(mark_target_live_regs): Likewise.
> 	* sched-deps.c (get_implicit_reg_pending_clobbers): Likewise.
> 	* sel-sched.c (mark_unavailable_hard_regs): Likewise.
> 	(implicit_clobber_conflict_p): Likewise.
> 	* shrink-wrap.c (requires_stack_frame_p): Likewise.
> 	(try_shrink_wrapping): Likewise.
OK
jeff

Patch
diff mbox series

Index: gcc/hard-reg-set.h
===================================================================
--- gcc/hard-reg-set.h	2019-09-09 16:08:54.788113807 +0100
+++ gcc/hard-reg-set.h	2019-09-09 16:10:15.303545844 +0100
@@ -127,8 +127,8 @@  #define HARD_CONST(X) ((HARD_REG_ELT_TYP
    These take just one argument.
 
    Also define:
-   IOR_COMPL_HARD_REG_SET and AND_COMPL_HARD_REG_SET
-   These take two arguments TO and FROM; they read from FROM
+   IOR_COMPL_HARD_REG_SET
+   This takes two arguments TO and FROM; it reads from FROM
    and combines its complement bitwise into TO.
 
    Also define:
@@ -153,7 +153,6 @@  #define CLEAR_HARD_REG_SET(TO) ((TO) = H
 #define SET_HARD_REG_SET(TO) ((TO) = ~ HARD_CONST (0))
 
 #define IOR_COMPL_HARD_REG_SET(TO, FROM) ((TO) |= ~ (FROM))
-#define AND_COMPL_HARD_REG_SET(TO, FROM) ((TO) &= ~ (FROM))
 
 static inline bool
 hard_reg_set_subset_p (const_hard_reg_set x, const_hard_reg_set y)
@@ -217,13 +216,6 @@  SET_HARD_REG_SET (HARD_REG_SET &set)
 }
 
 inline void
-AND_COMPL_HARD_REG_SET (HARD_REG_SET &to, const_hard_reg_set from)
-{
-  for (unsigned int i = 0; i < ARRAY_SIZE (to.elts); ++i)
-    to.elts[i] &= ~from.elts[i];
-}
-
-inline void
 IOR_COMPL_HARD_REG_SET (HARD_REG_SET &to, const_hard_reg_set from)
 {
   for (unsigned int i = 0; i < ARRAY_SIZE (to.elts); ++i)
Index: gcc/caller-save.c
===================================================================
--- gcc/caller-save.c	2019-09-09 16:07:28.364726810 +0100
+++ gcc/caller-save.c	2019-09-09 16:10:15.291545927 +0100
@@ -455,8 +455,7 @@  setup_save_areas (void)
       if (SIBLING_CALL_P (insn) && crtl->return_rtx)
 	mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets);
 
-      AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set);
-      AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets);
+      used_regs &= ~(call_fixed_reg_set | this_insn_sets);
       hard_regs_to_save &= used_regs;
       for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
 	if (TEST_HARD_REG_BIT (hard_regs_to_save, regno))
@@ -540,8 +539,7 @@  setup_save_areas (void)
 	  if (SIBLING_CALL_P (insn) && crtl->return_rtx)
 	    mark_set_regs (crtl->return_rtx, NULL_RTX, &this_insn_sets);
 
-	  AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set);
-	  AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets);
+	  used_regs &= ~(call_fixed_reg_set | this_insn_sets);
 	  hard_regs_to_save &= used_regs;
 	  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
 	    if (TEST_HARD_REG_BIT (hard_regs_to_save, regno))
@@ -796,7 +794,7 @@  save_call_clobbered_regs (void)
 		 afterwards.  */
 	      CLEAR_HARD_REG_SET (this_insn_sets);
 	      note_stores (insn, mark_set_regs, &this_insn_sets);
-	      AND_COMPL_HARD_REG_SET (hard_regs_saved, this_insn_sets);
+	      hard_regs_saved &= ~this_insn_sets;
 	    }
 
 	  if (code == CALL_INSN
@@ -852,9 +850,9 @@  save_call_clobbered_regs (void)
 	      note_stores (insn, mark_set_regs, &this_insn_sets);
 
 	      /* Compute which hard regs must be saved before this call.  */
-	      AND_COMPL_HARD_REG_SET (hard_regs_to_save, call_fixed_reg_set);
-	      AND_COMPL_HARD_REG_SET (hard_regs_to_save, this_insn_sets);
-	      AND_COMPL_HARD_REG_SET (hard_regs_to_save, hard_regs_saved);
+	      hard_regs_to_save &= ~(call_fixed_reg_set
+				     | this_insn_sets
+				     | hard_regs_saved);
 	      get_call_reg_set_usage (insn, &call_def_reg_set,
 				      call_used_reg_set);
 	      hard_regs_to_save &= call_def_reg_set;
Index: gcc/config/epiphany/epiphany.c
===================================================================
--- gcc/config/epiphany/epiphany.c	2019-09-09 16:06:17.629228543 +0100
+++ gcc/config/epiphany/epiphany.c	2019-09-09 16:10:15.291545927 +0100
@@ -2242,7 +2242,7 @@  epiphany_conditional_register_usage (voi
     CLEAR_HARD_REG_SET (reg_class_contents[SHORT_INSN_REGS]);
   reg_class_contents[SIBCALL_REGS] = reg_class_contents[GENERAL_REGS];
   /* It would be simpler and quicker if we could just use
-     AND_COMPL_HARD_REG_SET, alas, call_used_reg_set is yet uninitialized;
+     &~, alas, call_used_reg_set is yet uninitialized;
      it is set up later by our caller.  */
   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
     if (!call_used_regs[i])
Index: gcc/config/frv/frv.c
===================================================================
--- gcc/config/frv/frv.c	2019-09-09 16:06:17.633228515 +0100
+++ gcc/config/frv/frv.c	2019-09-09 16:10:15.291545927 +0100
@@ -5201,8 +5201,7 @@  frv_ifcvt_modify_tests (ce_if_block *ce_
      not fixed.  However, allow the ICC/ICR temporary registers to be allocated
      if we did not need to use them in reloading other registers.  */
   memset (&tmp_reg->regs, 0, sizeof (tmp_reg->regs));
-  tmp_reg->regs = call_used_reg_set;
-  AND_COMPL_HARD_REG_SET (tmp_reg->regs, fixed_reg_set);
+  tmp_reg->regs = call_used_reg_set &~ fixed_reg_set;
   SET_HARD_REG_BIT (tmp_reg->regs, ICC_TEMP);
   SET_HARD_REG_BIT (tmp_reg->regs, ICR_TEMP);
 
@@ -5311,7 +5310,7 @@  frv_ifcvt_modify_tests (ce_if_block *ce_
 
 	      CLEAR_HARD_REG_SET (mentioned_regs);
 	      find_all_hard_regs (PATTERN (insn), &mentioned_regs);
-	      AND_COMPL_HARD_REG_SET (tmp_reg->regs, mentioned_regs);
+	      tmp_reg->regs &= ~mentioned_regs;
 
 	      pattern = PATTERN (insn);
 	      if (GET_CODE (pattern) == COND_EXEC)
@@ -5347,8 +5346,7 @@  frv_ifcvt_modify_tests (ce_if_block *ce_
 		}
 
 	      if (! skip_nested_if)
-		AND_COMPL_HARD_REG_SET (frv_ifcvt.nested_cc_ok_rewrite,
-					mentioned_regs);
+		frv_ifcvt.nested_cc_ok_rewrite &= ~mentioned_regs;
 	    }
 
 	  if (insn == last_insn)
Index: gcc/config/gcn/gcn.c
===================================================================
--- gcc/config/gcn/gcn.c	2019-09-09 16:08:54.784113835 +0100
+++ gcc/config/gcn/gcn.c	2019-09-09 16:10:15.295545899 +0100
@@ -4628,7 +4628,7 @@  gcn_md_reorg (void)
 	  prev_insn->age += 1 + nops_rqd;
 
 	  written |= iwrites;
-	  AND_COMPL_HARD_REG_SET (prev_insn->writes, written);
+	  prev_insn->writes &= ~written;
 	}
 
       /* Track the current instruction as a previous instruction.  */
Index: gcc/config/i386/i386.c
===================================================================
--- gcc/config/i386/i386.c	2019-09-09 12:27:14.250372346 +0100
+++ gcc/config/i386/i386.c	2019-09-09 16:10:15.299545870 +0100
@@ -497,18 +497,15 @@  ix86_conditional_register_usage (void)
 
   /* If MMX is disabled, disable the registers.  */
   if (! TARGET_MMX)
-    AND_COMPL_HARD_REG_SET (accessible_reg_set,
-			    reg_class_contents[(int) MMX_REGS]);
+    accessible_reg_set &= ~reg_class_contents[MMX_REGS];
 
   /* If SSE is disabled, disable the registers.  */
   if (! TARGET_SSE)
-    AND_COMPL_HARD_REG_SET (accessible_reg_set,
-			    reg_class_contents[(int) ALL_SSE_REGS]);
+    accessible_reg_set &= ~reg_class_contents[ALL_SSE_REGS];
 
   /* If the FPU is disabled, disable the registers.  */
   if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
-    AND_COMPL_HARD_REG_SET (accessible_reg_set,
-			    reg_class_contents[(int) FLOAT_REGS]);
+    accessible_reg_set &= ~reg_class_contents[FLOAT_REGS];
 
   /* If AVX512F is disabled, disable the registers.  */
   if (! TARGET_AVX512F)
@@ -516,8 +513,7 @@  ix86_conditional_register_usage (void)
       for (i = FIRST_EXT_REX_SSE_REG; i <= LAST_EXT_REX_SSE_REG; i++)
 	CLEAR_HARD_REG_BIT (accessible_reg_set, i);
 
-      AND_COMPL_HARD_REG_SET (accessible_reg_set,
-			      reg_class_contents[(int) ALL_MASK_REGS]);
+      accessible_reg_set &= ~reg_class_contents[ALL_MASK_REGS];
     }
 }
 
Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c	2019-09-09 16:06:17.641228458 +0100
+++ gcc/config/mips/mips.c	2019-09-09 16:10:15.299545870 +0100
@@ -12981,7 +12981,7 @@  mips_class_max_nregs (enum reg_class rcl
       if (mips_hard_regno_mode_ok (ST_REG_FIRST, mode))
 	size = MIN (size, 4);
 
-      AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
+      left &= ~reg_class_contents[ST_REGS];
     }
   if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
     {
@@ -12993,7 +12993,7 @@  mips_class_max_nregs (enum reg_class rcl
 	    size = MIN (size, UNITS_PER_FPREG);
 	}
 
-      AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
+      left &= ~reg_class_contents[FP_REGS];
     }
   if (!hard_reg_set_empty_p (left))
     size = MIN (size, UNITS_PER_WORD);
@@ -20431,27 +20431,20 @@  mips_conditional_register_usage (void)
       global_regs[CCDSP_SC_REGNUM] = 1;
     }
   else
-    AND_COMPL_HARD_REG_SET (accessible_reg_set,
-			    reg_class_contents[(int) DSP_ACC_REGS]);
+    accessible_reg_set &= ~reg_class_contents[DSP_ACC_REGS];
 
   if (!ISA_HAS_HILO)
-    AND_COMPL_HARD_REG_SET (accessible_reg_set,
-			    reg_class_contents[(int) MD_REGS]);
+    accessible_reg_set &= ~reg_class_contents[MD_REGS];
 
   if (!TARGET_HARD_FLOAT)
-    {
-      AND_COMPL_HARD_REG_SET (accessible_reg_set,
-			      reg_class_contents[(int) FP_REGS]);
-      AND_COMPL_HARD_REG_SET (accessible_reg_set,
-			      reg_class_contents[(int) ST_REGS]);
-    }
+    accessible_reg_set &= ~(reg_class_contents[FP_REGS]
+			    | reg_class_contents[ST_REGS]);
   else if (!ISA_HAS_8CC)
     {
       /* We only have a single condition-code register.  We implement
 	 this by fixing all the condition-code registers and generating
 	 RTL that refers directly to ST_REG_FIRST.  */
-      AND_COMPL_HARD_REG_SET (accessible_reg_set,
-			      reg_class_contents[(int) ST_REGS]);
+      accessible_reg_set &= ~reg_class_contents[ST_REGS];
       if (!ISA_HAS_CCF)
 	SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
       fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
@@ -20493,8 +20486,7 @@  mips_conditional_register_usage (void)
       /* Do not allow HI and LO to be treated as register operands.
 	 There are no MTHI or MTLO instructions (or any real need
 	 for them) and one-way registers cannot easily be reloaded.  */
-      AND_COMPL_HARD_REG_SET (operand_reg_set,
-			      reg_class_contents[(int) MD_REGS]);
+      operand_reg_set &= ~reg_class_contents[MD_REGS];
     }
   /* $f20-$f23 are call-clobbered for n64.  */
   if (mips_abi == ABI_64)
Index: gcc/config/sh/sh.c
===================================================================
--- gcc/config/sh/sh.c	2019-09-09 16:06:54.720965449 +0100
+++ gcc/config/sh/sh.c	2019-09-09 16:10:15.303545844 +0100
@@ -6707,9 +6707,7 @@  output_stack_adjust (int size, rtx reg,
 	    temp = -1;
 	  if (temp < 0 && ! current_function_interrupt && epilogue_p >= 0)
 	    {
-	      HARD_REG_SET temps;
-	      temps = call_used_reg_set;
-	      AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
+	      HARD_REG_SET temps = call_used_reg_set & ~call_fixed_reg_set;
 	      if (epilogue_p > 0)
 		{
 		  int nreg = 0;
Index: gcc/ira-color.c
===================================================================
--- gcc/ira-color.c	2019-09-09 16:08:54.792113779 +0100
+++ gcc/ira-color.c	2019-09-09 16:10:15.303545844 +0100
@@ -716,8 +716,7 @@  form_allocno_hard_regs_nodes_forest (voi
 	    (allocno_data->profitable_hard_regs,
 	     ALLOCNO_MEMORY_COST (a) - ALLOCNO_CLASS_COST (a)));
     }
-  SET_HARD_REG_SET (temp);
-  AND_COMPL_HARD_REG_SET (temp, ira_no_alloc_regs);
+  temp = ~ira_no_alloc_regs;
   add_allocno_hard_regs (temp, 0);
   qsort (allocno_hard_regs_vec.address () + start,
 	 allocno_hard_regs_vec.length () - start,
@@ -1047,8 +1046,8 @@  setup_profitable_hard_regs (void)
 	    {
 	      ira_object_t obj = ALLOCNO_OBJECT (a, k);
 	      
-	      AND_COMPL_HARD_REG_SET (data->profitable_hard_regs,
-				      OBJECT_TOTAL_CONFLICT_HARD_REGS (obj));
+	      data->profitable_hard_regs
+		&= ~OBJECT_TOTAL_CONFLICT_HARD_REGS (obj);
 	    }
 	}
     }
@@ -1089,9 +1088,8 @@  setup_profitable_hard_regs (void)
 		       hard_regno + num);
 		}
 	      else
-		AND_COMPL_HARD_REG_SET
-		  (ALLOCNO_COLOR_DATA (conflict_a)->profitable_hard_regs,
-		   ira_reg_mode_hard_regset[hard_regno][mode]);
+		ALLOCNO_COLOR_DATA (conflict_a)->profitable_hard_regs
+		  &= ~ira_reg_mode_hard_regset[hard_regno][mode];
 	    }
 	}
     }
@@ -1590,12 +1588,10 @@  get_conflict_and_start_profitable_regs (
       conflict_regs[i] = OBJECT_TOTAL_CONFLICT_HARD_REGS (obj);
     }
   if (retry_p)
-    {
-      *start_profitable_regs = reg_class_contents[ALLOCNO_CLASS (a)];
-      AND_COMPL_HARD_REG_SET (*start_profitable_regs,
-			      ira_prohibited_class_mode_regs
-			      [ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]);
-    }
+    *start_profitable_regs
+      = (reg_class_contents[ALLOCNO_CLASS (a)]
+	 &~ (ira_prohibited_class_mode_regs
+	     [ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)]));
   else
     *start_profitable_regs = ALLOCNO_COLOR_DATA (a)->profitable_hard_regs;
 }
Index: gcc/ira-conflicts.c
===================================================================
--- gcc/ira-conflicts.c	2019-09-09 16:08:54.792113779 +0100
+++ gcc/ira-conflicts.c	2019-09-09 16:10:15.303545844 +0100
@@ -660,15 +660,15 @@  print_allocno_conflicts (FILE * file, bo
 	      putc (')', file);
 	    }
 	}
-      conflicting_hard_regs = OBJECT_TOTAL_CONFLICT_HARD_REGS (obj);
-      AND_COMPL_HARD_REG_SET (conflicting_hard_regs, ira_no_alloc_regs);
-      conflicting_hard_regs &= reg_class_contents[ALLOCNO_CLASS (a)];
+      conflicting_hard_regs = (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)
+			       & ~ira_no_alloc_regs
+			       & reg_class_contents[ALLOCNO_CLASS (a)]);
       print_hard_reg_set (file, "\n;;     total conflict hard regs:",
 			  conflicting_hard_regs);
 
-      conflicting_hard_regs = OBJECT_CONFLICT_HARD_REGS (obj);
-      AND_COMPL_HARD_REG_SET (conflicting_hard_regs, ira_no_alloc_regs);
-      conflicting_hard_regs &= reg_class_contents[ALLOCNO_CLASS (a)];
+      conflicting_hard_regs = (OBJECT_CONFLICT_HARD_REGS (obj)
+			       & ~ira_no_alloc_regs
+			       & reg_class_contents[ALLOCNO_CLASS (a)]);
       print_hard_reg_set (file, ";;     conflict hard regs:",
 			  conflicting_hard_regs);
       putc ('\n', file);
@@ -738,11 +738,9 @@  ira_build_conflicts (void)
   if (! targetm.class_likely_spilled_p (base))
     CLEAR_HARD_REG_SET (temp_hard_reg_set);
   else
-    {
-      temp_hard_reg_set = reg_class_contents[base];
-      AND_COMPL_HARD_REG_SET (temp_hard_reg_set, ira_no_alloc_regs);
-      temp_hard_reg_set &= call_used_reg_set;
-    }
+    temp_hard_reg_set = (reg_class_contents[base]
+			 & ~ira_no_alloc_regs
+			 & call_used_reg_set);
   FOR_EACH_ALLOCNO (a, ai)
     {
       int i, n = ALLOCNO_NUM_OBJECTS (a);
Index: gcc/ira-costs.c
===================================================================
--- gcc/ira-costs.c	2019-09-09 16:07:28.372726754 +0100
+++ gcc/ira-costs.c	2019-09-09 16:10:15.303545844 +0100
@@ -255,9 +255,8 @@  restrict_cost_classes (cost_classes_t fu
       /* Calculate the set of registers in CL that belong to REGS and
 	 are valid for MODE.  */
       HARD_REG_SET valid_for_cl = reg_class_contents[cl] & regs;
-      AND_COMPL_HARD_REG_SET (valid_for_cl,
-			      ira_prohibited_class_mode_regs[cl][mode]);
-      AND_COMPL_HARD_REG_SET (valid_for_cl, ira_no_alloc_regs);
+      valid_for_cl &= ~(ira_prohibited_class_mode_regs[cl][mode]
+			| ira_no_alloc_regs);
       if (hard_reg_set_empty_p (valid_for_cl))
 	continue;
 
@@ -341,8 +340,7 @@  setup_regno_cost_classes_by_aclass (int
 
   if ((classes_ptr = cost_classes_aclass_cache[aclass]) == NULL)
     {
-      temp = reg_class_contents[aclass];
-      AND_COMPL_HARD_REG_SET (temp, ira_no_alloc_regs);
+      temp = reg_class_contents[aclass] & ~ira_no_alloc_regs;
       /* We exclude classes from consideration which are subsets of
 	 ACLASS only if ACLASS is an uniform class.  */
       exclude_p = ira_uniform_class_p[aclass];
@@ -354,8 +352,7 @@  setup_regno_cost_classes_by_aclass (int
 	    {
 	      /* Exclude non-uniform classes which are subsets of
 		 ACLASS.  */
-	      temp2 = reg_class_contents[cl];
-	      AND_COMPL_HARD_REG_SET (temp2, ira_no_alloc_regs);
+	      temp2 = reg_class_contents[cl] & ~ira_no_alloc_regs;
 	      if (hard_reg_set_subset_p (temp2, temp) && cl != aclass)
 		continue;
 	    }
Index: gcc/ira-lives.c
===================================================================
--- gcc/ira-lives.c	2019-09-09 16:08:54.792113779 +0100
+++ gcc/ira-lives.c	2019-09-09 16:10:15.303545844 +0100
@@ -1129,8 +1129,7 @@  process_bb_node_lives (ira_loop_tree_nod
       reg_live_out = df_get_live_out (bb);
       sparseset_clear (objects_live);
       REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out);
-      AND_COMPL_HARD_REG_SET (hard_regs_live, eliminable_regset);
-      AND_COMPL_HARD_REG_SET (hard_regs_live, ira_no_alloc_regs);
+      hard_regs_live &= ~(eliminable_regset | ira_no_alloc_regs);
       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 	if (TEST_HARD_REG_BIT (hard_regs_live, i))
 	  {
Index: gcc/ira.c
===================================================================
--- gcc/ira.c	2019-09-09 16:08:54.792113779 +0100
+++ gcc/ira.c	2019-09-09 16:10:15.307545816 +0100
@@ -471,8 +471,7 @@  setup_class_hard_regs (void)
   ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER);
   for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
     {
-      temp_hard_regset = reg_class_contents[cl];
-      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+      temp_hard_regset = reg_class_contents[cl] & ~no_unit_alloc_regs;
       CLEAR_HARD_REG_SET (processed_hard_reg_set);
       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 	{
@@ -541,8 +540,7 @@  setup_reg_subclasses (void)
       if (i == (int) NO_REGS)
 	continue;
 
-      temp_hard_regset = reg_class_contents[i];
-      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+      temp_hard_regset = reg_class_contents[i] & ~no_unit_alloc_regs;
       if (hard_reg_set_empty_p (temp_hard_regset))
 	continue;
       for (j = 0; j < N_REG_CLASSES; j++)
@@ -550,8 +548,7 @@  setup_reg_subclasses (void)
 	  {
 	    enum reg_class *p;
 
-	    temp_hard_regset2 = reg_class_contents[j];
-	    AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
+	    temp_hard_regset2 = reg_class_contents[j] & ~no_unit_alloc_regs;
 	    if (! hard_reg_set_subset_p (temp_hard_regset,
 					 temp_hard_regset2))
 	      continue;
@@ -605,10 +602,8 @@  setup_class_subset_and_memory_move_costs
   for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
     for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--)
       {
-	temp_hard_regset = reg_class_contents[cl];
-	AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-	temp_hard_regset2 = reg_class_contents[cl2];
-	AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
+	temp_hard_regset = reg_class_contents[cl] & ~no_unit_alloc_regs;
+	temp_hard_regset2 = reg_class_contents[cl2] & ~no_unit_alloc_regs;
 	ira_class_subset_p[cl][cl2]
 	  = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2);
 	if (! hard_reg_set_empty_p (temp_hard_regset2)
@@ -815,10 +810,10 @@  setup_pressure_classes (void)
 		 register pressure class.  */
 	      for (m = 0; m < NUM_MACHINE_MODES; m++)
 		{
-		  temp_hard_regset = reg_class_contents[cl];
-		  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-		  AND_COMPL_HARD_REG_SET (temp_hard_regset,
-					  ira_prohibited_class_mode_regs[cl][m]);
+		  temp_hard_regset
+		    = (reg_class_contents[cl]
+		       & ~(no_unit_alloc_regs
+			   | ira_prohibited_class_mode_regs[cl][m]));
 		  if (hard_reg_set_empty_p (temp_hard_regset))
 		    continue;
 		  ira_init_register_move_cost_if_necessary ((machine_mode) m);
@@ -832,8 +827,7 @@  setup_pressure_classes (void)
 	    }
 	  curr = 0;
 	  insert_p = true;
-	  temp_hard_regset = reg_class_contents[cl];
-	  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+	  temp_hard_regset = reg_class_contents[cl] & ~no_unit_alloc_regs;
 	  /* Remove so far added pressure classes which are subset of the
 	     current candidate class.  Prefer GENERAL_REGS as a pressure
 	     register class to another class containing the same
@@ -844,8 +838,8 @@  setup_pressure_classes (void)
 	  for (i = 0; i < n; i++)
 	    {
 	      cl2 = pressure_classes[i];
-	      temp_hard_regset2 = reg_class_contents[cl2];
-	      AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
+	      temp_hard_regset2 = (reg_class_contents[cl2]
+				   & ~no_unit_alloc_regs);
 	      if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2)
 		  && (! hard_reg_set_equal_p (temp_hard_regset,
 					      temp_hard_regset2)
@@ -907,8 +901,8 @@  setup_pressure_classes (void)
 	 for which no reg class is defined.  */
       if (REGNO_REG_CLASS (i) == NO_REGS)
 	SET_HARD_REG_BIT (ignore_hard_regs, i);
-    AND_COMPL_HARD_REG_SET (temp_hard_regset, ignore_hard_regs);
-    AND_COMPL_HARD_REG_SET (temp_hard_regset2, ignore_hard_regs);
+    temp_hard_regset &= ~ignore_hard_regs;
+    temp_hard_regset2 &= ~ignore_hard_regs;
     ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset));
   }
 #endif
@@ -1000,14 +994,11 @@  setup_allocno_and_important_classes (voi
      same set of hard registers.  */
   for (i = 0; i < LIM_REG_CLASSES; i++)
     {
-      temp_hard_regset = reg_class_contents[i];
-      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+      temp_hard_regset = reg_class_contents[i] & ~no_unit_alloc_regs;
       for (j = 0; j < n; j++)
 	{
 	  cl = classes[j];
-	  temp_hard_regset2 = reg_class_contents[cl];
-	  AND_COMPL_HARD_REG_SET (temp_hard_regset2,
-				  no_unit_alloc_regs);
+	  temp_hard_regset2 = reg_class_contents[cl] & ~no_unit_alloc_regs;
 	  if (hard_reg_set_equal_p (temp_hard_regset,
 				    temp_hard_regset2))
 	    break;
@@ -1036,13 +1027,12 @@  setup_allocno_and_important_classes (voi
   for (cl = 0; cl < N_REG_CLASSES; cl++)
     if (ira_class_hard_regs_num[cl] > 0)
       {
-	temp_hard_regset = reg_class_contents[cl];
-	AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+	temp_hard_regset = reg_class_contents[cl] & ~no_unit_alloc_regs;
 	set_p = false;
 	for (j = 0; j < ira_allocno_classes_num; j++)
 	  {
-	    temp_hard_regset2 = reg_class_contents[ira_allocno_classes[j]];
-	    AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs);
+	    temp_hard_regset2 = (reg_class_contents[ira_allocno_classes[j]]
+				 & ~no_unit_alloc_regs);
 	    if ((enum reg_class) cl == ira_allocno_classes[j])
 	      break;
 	    else if (hard_reg_set_subset_p (temp_hard_regset,
@@ -1117,8 +1107,8 @@  setup_class_translate_array (enum reg_cl
 	{
 	  aclass = classes[i];
 	  temp_hard_regset = (reg_class_contents[aclass]
-			      & reg_class_contents[cl]);
-	  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+			      & reg_class_contents[cl]
+			      & ~no_unit_alloc_regs);
 	  if (! hard_reg_set_empty_p (temp_hard_regset))
 	    {
 	      min_cost = INT_MAX;
@@ -1220,10 +1210,8 @@  setup_reg_class_relations (void)
 	  ira_reg_classes_intersect_p[cl1][cl2] = false;
 	  ira_reg_class_intersect[cl1][cl2] = NO_REGS;
 	  ira_reg_class_subset[cl1][cl2] = NO_REGS;
-	  temp_hard_regset = reg_class_contents[cl1];
-	  AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
-	  temp_set2 = reg_class_contents[cl2];
-	  AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
+	  temp_hard_regset = reg_class_contents[cl1] & ~no_unit_alloc_regs;
+	  temp_set2 = reg_class_contents[cl2] & ~no_unit_alloc_regs;
 	  if (hard_reg_set_empty_p (temp_hard_regset)
 	      && hard_reg_set_empty_p (temp_set2))
 	    {
@@ -1262,14 +1250,13 @@  setup_reg_class_relations (void)
 	  ira_reg_class_subunion[cl1][cl2] = NO_REGS;
 	  ira_reg_class_superunion[cl1][cl2] = NO_REGS;
 	  intersection_set = (reg_class_contents[cl1]
-			      & reg_class_contents[cl2]);
-	  AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs);
-	  union_set = reg_class_contents[cl1] | reg_class_contents[cl2];
-	  AND_COMPL_HARD_REG_SET (union_set, no_unit_alloc_regs);
+			      & reg_class_contents[cl2]
+			      & ~no_unit_alloc_regs);
+	  union_set = ((reg_class_contents[cl1] | reg_class_contents[cl2])
+		       & ~no_unit_alloc_regs);
 	  for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++)
 	    {
-	      temp_hard_regset = reg_class_contents[cl3];
-	      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+	      temp_hard_regset = reg_class_contents[cl3] & ~no_unit_alloc_regs;
 	      if (hard_reg_set_subset_p (temp_hard_regset, intersection_set))
 		{
 		  /* CL3 allocatable hard register set is inside of
@@ -1280,7 +1267,7 @@  setup_reg_class_relations (void)
 		      temp_set2
 			= (reg_class_contents
 			   [ira_reg_class_intersect[cl1][cl2]]);
-		      AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
+		      temp_set2 &= ~no_unit_alloc_regs;
 		      if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2)
 			  /* If the allocatable hard register sets are
 			     the same, prefer GENERAL_REGS or the
@@ -1298,8 +1285,8 @@  setup_reg_class_relations (void)
 			ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3;
 		    }
 		  temp_set2
-		    = reg_class_contents[ira_reg_class_subset[cl1][cl2]];
-		  AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
+		    = (reg_class_contents[ira_reg_class_subset[cl1][cl2]]
+		       & ~no_unit_alloc_regs);
 		  if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2)
 		      /* Ignore unavailable hard registers and prefer
 			 smallest class for debugging purposes.  */
@@ -1317,8 +1304,8 @@  setup_reg_class_relations (void)
 		     union of allocatable hard register sets of CL1
 		     and CL2.  */
 		  temp_set2
-		    = reg_class_contents[ira_reg_class_subunion[cl1][cl2]];
-		  AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
+		    = (reg_class_contents[ira_reg_class_subunion[cl1][cl2]]
+		       & ~no_unit_alloc_regs);
 	 	  if (ira_reg_class_subunion[cl1][cl2] == NO_REGS
 		      || (hard_reg_set_subset_p (temp_set2, temp_hard_regset)
 			  
@@ -1341,8 +1328,8 @@  setup_reg_class_relations (void)
 		     of allocatable hard register sets of CL1 and
 		     CL2.  */
 		  temp_set2
-		    = reg_class_contents[ira_reg_class_superunion[cl1][cl2]];
-		  AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs);
+		    = (reg_class_contents[ira_reg_class_superunion[cl1][cl2]]
+		       & ~no_unit_alloc_regs);
 	 	  if (ira_reg_class_superunion[cl1][cl2] == NO_REGS
 		      || (hard_reg_set_subset_p (temp_hard_regset, temp_set2)
 
@@ -1491,8 +1478,7 @@  setup_prohibited_class_mode_regs (void)
 
   for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
     {
-      temp_hard_regset = reg_class_contents[cl];
-      AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
+      temp_hard_regset = reg_class_contents[cl] & ~no_unit_alloc_regs;
       for (j = 0; j < NUM_MACHINE_MODES; j++)
 	{
 	  count = 0;
Index: gcc/lra-assigns.c
===================================================================
--- gcc/lra-assigns.c	2019-09-09 16:08:54.792113779 +0100
+++ gcc/lra-assigns.c	2019-09-09 16:10:15.307545816 +0100
@@ -619,8 +619,7 @@  find_hard_regno_for_1 (int regno, int *c
   biggest_nregs = hard_regno_nregs (hard_regno, biggest_mode);
   nregs_diff = (biggest_nregs
 		- hard_regno_nregs (hard_regno, PSEUDO_REGNO_MODE (regno)));
-  available_regs = reg_class_contents[rclass];
-  AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs);
+  available_regs = reg_class_contents[rclass] & ~lra_no_alloc_regs;
   for (i = 0; i < rclass_size; i++)
     {
       if (try_only_hard_regno >= 0)
Index: gcc/lra-constraints.c
===================================================================
--- gcc/lra-constraints.c	2019-09-09 16:08:54.796113751 +0100
+++ gcc/lra-constraints.c	2019-09-09 16:10:15.307545816 +0100
@@ -1854,8 +1854,7 @@  prohibited_class_reg_set_mode_p (enum re
   HARD_REG_SET temp;
   
   lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set));
-  temp = set;
-  AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs);
+  temp = set & ~lra_no_alloc_regs;
   return (hard_reg_set_subset_p
 	  (temp, ira_prohibited_class_mode_regs[rclass][mode]));
 }
@@ -2513,13 +2512,11 @@  process_alt_operands (int only_alternati
 
 	      if (this_alternative != NO_REGS)
 		{
-		  HARD_REG_SET available_regs;
-		  
-		  available_regs = reg_class_contents[this_alternative];
-		  AND_COMPL_HARD_REG_SET
-		    (available_regs,
-		     ira_prohibited_class_mode_regs[this_alternative][mode]);
-		  AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs);
+		  HARD_REG_SET available_regs
+		    = (reg_class_contents[this_alternative]
+		       & ~((ira_prohibited_class_mode_regs
+			    [this_alternative][mode])
+			   | lra_no_alloc_regs));
 		  if (hard_reg_set_empty_p (available_regs))
 		    {
 		      /* There are no hard regs holding a value of given
@@ -6407,8 +6404,8 @@  inherit_in_ebb (rtx_insn *head, rtx_insn
 		      else
 			add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno),
 					     reg_renumber[dst_regno]);
-		      AND_COMPL_HARD_REG_SET (live_hard_regs, s);
-		      AND_COMPL_HARD_REG_SET (potential_reload_hard_regs, s);
+		      live_hard_regs &= ~s;
+		      potential_reload_hard_regs &= ~s;
 		    }
 		  /* We should invalidate potential inheritance or
 		     splitting for the current insn usages to the next
Index: gcc/lra-eliminations.c
===================================================================
--- gcc/lra-eliminations.c	2019-09-09 16:08:54.796113751 +0100
+++ gcc/lra-eliminations.c	2019-09-09 16:10:15.307545816 +0100
@@ -1203,7 +1203,7 @@  update_reg_eliminate (bitmap insns_with_
 	  }
       }
   lra_no_alloc_regs |= temp_hard_reg_set;
-  AND_COMPL_HARD_REG_SET (eliminable_regset, temp_hard_reg_set);
+  eliminable_regset &= ~temp_hard_reg_set;
   spill_pseudos (temp_hard_reg_set);
   return result;
 }
Index: gcc/lra-lives.c
===================================================================
--- gcc/lra-lives.c	2019-09-09 16:08:54.796113751 +0100
+++ gcc/lra-lives.c	2019-09-09 16:10:15.307545816 +0100
@@ -671,7 +671,7 @@  process_bb_lives (basic_block bb, int &c
   sparseset_clear (pseudos_live_through_setjumps);
   CLEAR_HARD_REG_SET (last_call_used_reg_set);
   REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out);
-  AND_COMPL_HARD_REG_SET (hard_regs_live, eliminable_regset);
+  hard_regs_live &= ~eliminable_regset;
   EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi)
     {
       update_pseudo_point (j, curr_point, USE_POINT);
Index: gcc/reload1.c
===================================================================
--- gcc/reload1.c	2019-09-09 16:08:54.800113722 +0100
+++ gcc/reload1.c	2019-09-09 16:10:15.307545816 +0100
@@ -3929,7 +3929,7 @@  update_eliminables_and_spill (void)
   HARD_REG_SET to_spill;
   CLEAR_HARD_REG_SET (to_spill);
   update_eliminables (&to_spill);
-  AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
+  used_spill_regs &= ~to_spill;
 
   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
     if (TEST_HARD_REG_BIT (to_spill, i))
@@ -4783,8 +4783,8 @@  reload_as_needed (int live_known)
          be partially clobbered by the call.  */
       else if (CALL_P (insn))
 	{
-	  AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
-	  AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
+	  reg_reloaded_valid &= ~(call_used_reg_set
+				  | reg_reloaded_call_part_clobbered);
 
 	  /* If this is a call to a setjmp-type function, we must not
 	     reuse any reload reg contents across the call; that will
Index: gcc/resource.c
===================================================================
--- gcc/resource.c	2019-09-09 16:08:54.800113722 +0100
+++ gcc/resource.c	2019-09-09 16:10:15.307545816 +0100
@@ -450,8 +450,8 @@  find_dead_or_set_registers (rtx_insn *ta
 	case CODE_LABEL:
 	  /* After a label, any pending dead registers that weren't yet
 	     used can be made dead.  */
-	  AND_COMPL_HARD_REG_SET (pending_dead_regs, needed.regs);
-	  AND_COMPL_HARD_REG_SET (res->regs, pending_dead_regs);
+	  pending_dead_regs &= ~needed.regs;
+	  res->regs &= ~pending_dead_regs;
 	  CLEAR_HARD_REG_SET (pending_dead_regs);
 
 	  continue;
@@ -565,14 +565,12 @@  find_dead_or_set_registers (rtx_insn *ta
 		    }
 
 		  target_res = *res;
-		  scratch = target_set.regs;
-		  AND_COMPL_HARD_REG_SET (scratch, needed.regs);
-		  AND_COMPL_HARD_REG_SET (target_res.regs, scratch);
+		  scratch = target_set.regs & ~needed.regs;
+		  target_res.regs &= ~scratch;
 
 		  fallthrough_res = *res;
-		  scratch = set.regs;
-		  AND_COMPL_HARD_REG_SET (scratch, needed.regs);
-		  AND_COMPL_HARD_REG_SET (fallthrough_res.regs, scratch);
+		  scratch = set.regs & ~needed.regs;
+		  fallthrough_res.regs &= ~scratch;
 
 		  if (!ANY_RETURN_P (this_jump_insn->jump_label ()))
 		    find_dead_or_set_registers
@@ -601,9 +599,8 @@  find_dead_or_set_registers (rtx_insn *ta
       mark_referenced_resources (insn, &needed, true);
       mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL);
 
-      scratch = set.regs;
-      AND_COMPL_HARD_REG_SET (scratch, needed.regs);
-      AND_COMPL_HARD_REG_SET (res->regs, scratch);
+      scratch = set.regs & ~needed.regs;
+      res->regs &= ~scratch;
     }
 
   return jump_insn;
@@ -1048,8 +1045,7 @@  mark_target_live_regs (rtx_insn *insns,
 		  /* CALL clobbers all call-used regs that aren't fixed except
 		     sp, ap, and fp.  Do this before setting the result of the
 		     call live.  */
-		  AND_COMPL_HARD_REG_SET (current_live_regs,
-					  regs_invalidated_by_this_call);
+		  current_live_regs &= ~regs_invalidated_by_this_call;
 		}
 
 	      /* A CALL_INSN sets any global register live, since it may
@@ -1097,7 +1093,7 @@  mark_target_live_regs (rtx_insn *insns,
 
 	      /* A label clobbers the pending dead registers since neither
 		 reload nor jump will propagate a value across a label.  */
-	      AND_COMPL_HARD_REG_SET (current_live_regs, pending_dead_regs);
+	      current_live_regs &= ~pending_dead_regs;
 	      CLEAR_HARD_REG_SET (pending_dead_regs);
 
 	      /* We must conservatively assume that all registers that used
@@ -1160,8 +1156,7 @@  mark_target_live_regs (rtx_insn *insns,
 	{
 	  mark_referenced_resources (insn, &needed, true);
 
-	  scratch = needed.regs;
-	  AND_COMPL_HARD_REG_SET (scratch, set.regs);
+	  scratch = needed.regs & ~set.regs;
 	  new_resources.regs |= scratch;
 
 	  mark_set_resources (insn, &set, 0, MARK_SRC_DEST_CALL);
Index: gcc/sched-deps.c
===================================================================
--- gcc/sched-deps.c	2019-09-09 16:08:54.800113722 +0100
+++ gcc/sched-deps.c	2019-09-09 16:10:15.307545816 +0100
@@ -2885,7 +2885,7 @@  get_implicit_reg_pending_clobbers (HARD_
   preprocess_constraints (insn);
   alternative_mask preferred = get_preferred_alternatives (insn);
   ira_implicitly_set_insn_hard_regs (temp, preferred);
-  AND_COMPL_HARD_REG_SET (*temp, ira_no_alloc_regs);
+  *temp &= ~ira_no_alloc_regs;
 }
 
 /* Analyze an INSN with pattern X to find all dependencies.  */
Index: gcc/sel-sched.c
===================================================================
--- gcc/sel-sched.c	2019-09-09 16:08:54.804113694 +0100
+++ gcc/sel-sched.c	2019-09-09 16:10:15.311545787 +0100
@@ -1248,8 +1248,8 @@  mark_unavailable_hard_regs (def_t def, s
   /* Exclude registers that are partially call clobbered.  */
   if (def->crosses_call
       && !targetm.hard_regno_call_part_clobbered (NULL, regno, mode))
-    AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
-                            sel_hrd.regs_for_call_clobbered[mode]);
+    reg_rename_p->available_for_renaming
+      &= ~sel_hrd.regs_for_call_clobbered[mode];
 
   /* Leave only those that are ok to rename.  */
   EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
@@ -1270,8 +1270,7 @@  mark_unavailable_hard_regs (def_t def, s
                             cur_reg);
     }
 
-  AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
-                          reg_rename_p->unavailable_hard_regs);
+  reg_rename_p->available_for_renaming &= ~reg_rename_p->unavailable_hard_regs;
 
   /* Regno is always ok from the renaming part of view, but it really
      could be in *unavailable_hard_regs already, so set it here instead
@@ -2105,7 +2104,7 @@  implicit_clobber_conflict_p (insn_t thro
   preprocess_constraints (insn);
   alternative_mask prefrred = get_preferred_alternatives (insn);
   ira_implicitly_set_insn_hard_regs (&temp, prefrred);
-  AND_COMPL_HARD_REG_SET (temp, ira_no_alloc_regs);
+  temp &= ~ira_no_alloc_regs;
 
   /* If any implicit clobber registers intersect with regular ones in
      through_insn, we have a dependency and thus bail out.  */
Index: gcc/shrink-wrap.c
===================================================================
--- gcc/shrink-wrap.c	2019-09-09 16:08:54.804113694 +0100
+++ gcc/shrink-wrap.c	2019-09-09 16:10:15.311545787 +0100
@@ -76,7 +76,7 @@  requires_stack_frame_p (rtx_insn *insn,
     }
   if (hard_reg_set_intersect_p (hardregs, prologue_used))
     return true;
-  AND_COMPL_HARD_REG_SET (hardregs, call_used_reg_set);
+  hardregs &= ~call_used_reg_set;
   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
     if (TEST_HARD_REG_BIT (hardregs, regno)
 	&& df_regs_ever_live_p (regno))
@@ -687,7 +687,7 @@  try_shrink_wrapping (edge *entry_edge, r
 	HARD_REG_SET this_used;
 	CLEAR_HARD_REG_SET (this_used);
 	note_uses (&PATTERN (insn), record_hard_reg_uses, &this_used);
-	AND_COMPL_HARD_REG_SET (this_used, prologue_clobbered);
+	this_used &= ~prologue_clobbered;
 	prologue_used |= this_used;
 	note_stores (insn, record_hard_reg_sets, &prologue_clobbered);
       }