From patchwork Sat Sep 7 11:35:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 1159320 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="ejMPHeZ+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46QXS46wLMz9sPp for ; Sat, 7 Sep 2019 21:36:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389332AbfIGLfw (ORCPT ); Sat, 7 Sep 2019 07:35:52 -0400 Received: from mail.kernel.org ([198.145.29.99]:38082 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725947AbfIGLfw (ORCPT ); Sat, 7 Sep 2019 07:35:52 -0400 Received: from localhost.localdomain (unknown [194.230.155.145]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0DAC7218AF; Sat, 7 Sep 2019 11:35:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1567856150; bh=VOxfcQzwaHM0XiCY/XXEfAZTtrIlO4ZRE/buwNFjUxw=; h=From:To:Subject:Date:From; b=ejMPHeZ+1HnqQoRFodV1DvPkSbS+FqzcmIxBykf0WA1uM+9HbpjaRmMlaOpC9cJgL ZVOfVsg+SYi50sBYI2nOlLJZ4cYLNyb3CTrLZrjEl4huwCmVRExS83gOS/25v6oqRn p38pReB5ObKwZwQoK7QIUNdasAocnM3c68oh4ZX8= From: Krzysztof Kozlowski To: Rob Herring , Mark Rutland , Kukjin Kim , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: sram: Convert SRAM bindings to json-schema Date: Sat, 7 Sep 2019 13:35:41 +0200 Message-Id: <20190907113542.4096-1-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert generic mmio-sram bindings to DT schema format using json-schema. Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/sram/sram.txt | 80 ---------- .../devicetree/bindings/sram/sram.yaml | 138 ++++++++++++++++++ 2 files changed, 138 insertions(+), 80 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sram/sram.txt create mode 100644 Documentation/devicetree/bindings/sram/sram.yaml diff --git a/Documentation/devicetree/bindings/sram/sram.txt b/Documentation/devicetree/bindings/sram/sram.txt deleted file mode 100644 index e98908bd4227..000000000000 --- a/Documentation/devicetree/bindings/sram/sram.txt +++ /dev/null @@ -1,80 +0,0 @@ -Generic on-chip SRAM - -Simple IO memory regions to be managed by the genalloc API. - -Required properties: - -- compatible : mmio-sram or atmel,sama5d2-securam - -- reg : SRAM iomem address range - -Reserving sram areas: ---------------------- - -Each child of the sram node specifies a region of reserved memory. Each -child node should use a 'reg' property to specify a specific range of -reserved memory. - -Following the generic-names recommended practice, node names should -reflect the purpose of the node. Unit address (@
) should be -appended to the name. - -Required properties in the sram node: - -- #address-cells, #size-cells : should use the same values as the root node -- ranges : standard definition, should translate from local addresses - within the sram to bus addresses - -Optional properties in the sram node: - -- no-memory-wc : the flag indicating, that SRAM memory region has not to - be remapped as write combining. WC is used by default. - -Required properties in the area nodes: - -- reg : iomem address range, relative to the SRAM range - -Optional properties in the area nodes: - -- compatible : standard definition, should contain a vendor specific string - in the form ,[-] -- pool : indicates that the particular reserved SRAM area is addressable - and in use by another device or devices -- export : indicates that the reserved SRAM area may be accessed outside - of the kernel, e.g. by bootloader or userspace -- protect-exec : Same as 'pool' above but with the additional - constraint that code wil be run from the region and - that the memory is maintained as read-only, executable - during code execution. NOTE: This region must be page - aligned on start and end in order to properly allow - manipulation of the page attributes. -- label : the name for the reserved partition, if omitted, the label - is taken from the node name excluding the unit address. -- clocks : a list of phandle and clock specifier pair that controls the - single SRAM clock. - -Example: - -sram: sram@5c000000 { - compatible = "mmio-sram"; - reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x5c000000 0x40000>; - - smp-sram@100 { - compatible = "socvendor,smp-sram"; - reg = <0x100 0x50>; - }; - - device-sram@1000 { - reg = <0x1000 0x1000>; - pool; - }; - - exported@20000 { - reg = <0x20000 0x20000>; - export; - }; -}; diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml new file mode 100644 index 000000000000..0821cdb4cef9 --- /dev/null +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sram/sram.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic on-chip SRAM + +maintainers: + - FIXME + +description: |+ + Simple IO memory regions to be managed by the genalloc API. + + Each child of the sram node specifies a region of reserved memory. Each + child node should use a 'reg' property to specify a specific range of + reserved memory. + + Following the generic-names recommended practice, node names should + reflect the purpose of the node. Unit address (@
) should be + appended to the name. + +properties: + $nodename: + pattern: "^sram(@.*)?" + + compatible: + items: + - enum: + - mmio-sram + - atmel,sama5d2-securam + + reg: + maxItems: 1 + + "#address-cells": + description: Should use the same values as the root node. + + "#size-cells": + description: Should use the same values as the root node. + + ranges: + description: + Should translate from local addresses within the sram to bus addresses. + + no-memory-wc: + description: + The flag indicating, that SRAM memory region has not to be remapped + as write combining. WC is used by default. + type: boolean + + # TODO: additionalProperties: false + +patternProperties: + "^([a-z]*-)?sram@[a-f0-9]$": + type: object + description: + Each child of the sram node specifies a region of reserved memory. + properties: + reg: + description: + IO mem address range, relative to the SRAM range. + + compatible: + $ref: /schemas/types.yaml#/definitions/string + description: + Should contain a vendor specific string in the form + ,[-] + + pool: + description: + Indicates that the particular reserved SRAM area is addressable + and in use by another device or devices. + type: boolean + + export: + description: + Indicates that the reserved SRAM area may be accessed outside + of the kernel, e.g. by bootloader or userspace. + type: boolean + + protect-exec: + description: | + Same as 'pool' above but with the additional constraint that code + will be run from the region and that the memory is maintained as + read-only, executable during code execution. NOTE: This region must + be page aligned on start and end in order to properly allow + manipulation of the page attributes. + type: boolean + + label: + $ref: /schemas/types.yaml#/definitions/string + description: + The name for the reserved partition, if omitted, the label is taken + from the node name excluding the unit address. + + clocks: + description: + A list of phandle and clock specifier pair that controls the + single SRAM clock. + + # TODO: additionalProperties: false + + required: + - reg + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +examples: + - | + sram: sram@5c000000 { + compatible = "mmio-sram"; + reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x5c000000 0x40000>; + + smp-sram@100 { + compatible = "socvendor,smp-sram"; + reg = <0x100 0x50>; + }; + + device-sram@1000 { + reg = <0x1000 0x1000>; + pool; + }; + + exported@20000 { + reg = <0x20000 0x20000>; + export; + }; + };