[v8,22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes

Message ID	1567786819-22142-23-git-send-email-bmeng.cn@gmail.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Bin Meng <bmeng.cn@gmail.com> To: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 6 Sep 2019 09:20:09 -0700 Message-Id: <1567786819-22142-23-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1567786819-22142-1-git-send-email-bmeng.cn@gmail.com> References: <1567786819-22142-1-git-send-email-bmeng.cn@gmail.com> Subject: [Qemu-devel] [PATCH v8 22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	riscv: sifive_u: Improve the emulation fidelity of sifive_u machine \| expand [v8,00/32] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine [v8,02/32] riscv: sifive_test: Add reset functionality [v8,03/32] riscv: hw: Remove superfluous "linux, phandle" property [v8,04/32] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell [v8,05/32] riscv: hw: Remove not needed PLIC properties in device tree [v8,06/32] riscv: hw: Change create_fdt() to return void [v8,07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead [v8,08/32] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h [v8,10/32] riscv: sifive_u: Remove the unnecessary include of prci header [v8,11/32] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} [v8,12/32] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming [v8,13/32] riscv: sifive_e: prci: Update the PRCI register block size [v8,14/32] riscv: sifive_e: Drop sifive_mmio_emulate() [v8,15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines [v8,16/32] riscv: hart: Extract hart realize to a separate routine [v8,17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array [v8,18/32] riscv: sifive_u: Set the minimum number of cpus to 2 [v8,19/32] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC [v8,20/32] riscv: sifive_u: Update PLIC hart topology configuration string [v8,21/32] riscv: sifive: Implement PRCI model for FU540 [v8,22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes [v8,23/32] riscv: sifive_u: Add PRCI block to the SoC [v8,24/32] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes [v8,25/32] riscv: sifive_u: Update UART base addresses and IRQs [v8,26/32] riscv: sifive_u: Change UART node name in device tree [v8,27/32] riscv: roms: Update default bios for sifive_u machine [v8,28/32] riscv: sifive: Implement a model for SiFive FU540 OTP [v8,29/32] riscv: sifive_u: Instantiate OTP memory with a serial number [v8,30/32] riscv: sifive_u: Fix broken GEM support [v8,31/32] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet [v8,32/32] riscv: sifive_u: Update model and compatible strings in device tree

Message ID

1567786819-22142-23-git-send-email-bmeng.cn@gmail.com

State

New

Headers

From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Date: Fri,  6 Sep 2019 09:20:09 -0700
Message-Id: <1567786819-22142-23-git-send-email-bmeng.cn@gmail.com>
In-Reply-To: <1567786819-22142-1-git-send-email-bmeng.cn@gmail.com>
References: <1567786819-22142-1-git-send-email-bmeng.cn@gmail.com>
Subject: [Qemu-devel] [PATCH v8 22/32] riscv: sifive_u: Generate hfclk and
	rtcclk nodes
Precedence: list
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

riscv: sifive_u: Improve the emulation fidelity of sifive_u machine | expand

Commit Message

Bin Meng Sept. 6, 2019, 4:20 p.m. UTC

To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---

Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_u.c         | 23 +++++++++++++++++++++++
 include/hw/riscv/sifive_u.h |  2 ++
 2 files changed, 25 insertions(+)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 713c451..3ee6fcb 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -79,6 +79,7 @@  static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     char ethclk_names[] = "pclk\0hclk\0tx_clk";
     uint32_t plic_phandle, ethclk_phandle, phandle = 1;
     uint32_t uartclk_phandle;
+    uint32_t hfclk_phandle, rtcclk_phandle;
 
     fdt = s->fdt = create_device_tree(&s->fdt_size);
     if (!fdt) {
@@ -97,6 +98,28 @@  static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 
+    hfclk_phandle = phandle++;
+    nodename = g_strdup_printf("/hfclk");
+    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
+    qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
+    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+        SIFIVE_U_HFCLK_FREQ);
+    qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+    qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+    g_free(nodename);
+
+    rtcclk_phandle = phandle++;
+    nodename = g_strdup_printf("/rtcclk");
+    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
+    qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
+    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+        SIFIVE_U_RTCCLK_FREQ);
+    qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
+    qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
+    g_free(nodename);
+
     nodename = g_strdup_printf("/memory@%lx",
         (long)memmap[SIFIVE_U_DRAM].base);
     qemu_fdt_add_subnode(fdt, nodename);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 6b2b5b6..2441814 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -69,6 +69,8 @@  enum {
 
 enum {
     SIFIVE_U_CLOCK_FREQ = 1000000000,
+    SIFIVE_U_HFCLK_FREQ = 33333333,
+    SIFIVE_U_RTCCLK_FREQ = 1000000,
     SIFIVE_U_GEM_CLOCK_FREQ = 125000000
 };

[v8,22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes

Commit Message

Patch