From patchwork Thu Sep 22 08:53:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Jinsong" X-Patchwork-Id: 115907 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A0E15B6F81 for ; Thu, 22 Sep 2011 18:54:58 +1000 (EST) Received: from localhost ([::1]:37547 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R6f3S-0003Y9-RH for incoming@patchwork.ozlabs.org; Thu, 22 Sep 2011 04:54:50 -0400 Received: from eggs.gnu.org ([140.186.70.92]:41068) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R6f3L-0003Y4-5K for qemu-devel@nongnu.org; Thu, 22 Sep 2011 04:54:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R6f3K-0007xD-07 for qemu-devel@nongnu.org; Thu, 22 Sep 2011 04:54:43 -0400 Received: from mga14.intel.com ([143.182.124.37]:6233) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R6f3J-0007x1-FL for qemu-devel@nongnu.org; Thu, 22 Sep 2011 04:54:41 -0400 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga102.ch.intel.com with ESMTP; 22 Sep 2011 01:54:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="4.68,422,1312182000"; d="scan'208,223"; a="53012378" Received: from pgsmsx603.gar.corp.intel.com ([10.221.43.87]) by azsmga001.ch.intel.com with ESMTP; 22 Sep 2011 01:54:37 -0700 Received: from shsmsx602.ccr.corp.intel.com (10.239.4.104) by pgsmsx603.gar.corp.intel.com (10.221.43.87) with Microsoft SMTP Server (TLS) id 8.2.255.0; Thu, 22 Sep 2011 16:54:00 +0800 Received: from shsmsx502.ccr.corp.intel.com ([10.239.4.96]) by SHSMSX602.ccr.corp.intel.com ([10.239.4.104]) with mapi; Thu, 22 Sep 2011 16:53:59 +0800 From: "Liu, Jinsong" To: Avi Kivity , Marcelo Tosatti , "kvm@vger.kernel.org" , "qemu-devel@nongnu.org" Date: Thu, 22 Sep 2011 16:53:58 +0800 Thread-Topic: [PATCH] Add some pre-defination Thread-Index: Acx5BSqbIEn6YYgdRxijdp6ZkyqtVA== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 143.182.124.37 Cc: "Liu, Jinsong" , "Tian, Kevin" Subject: [Qemu-devel] [PATCH] Add some pre-defination X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From cab4eb79efc498abbda19c5b10c7d0858349af5f Mon Sep 17 00:00:00 2001 From: Liu, Jinsong Date: Thu, 22 Sep 2011 09:49:05 +0800 Subject: [PATCH 1/2] Add some pre-defination This pre-defination is preparing for KVM tsc deadline timer emulation, but theirself are no-kvm-specific. Signed-off-by: Liu, Jinsong --- arch/x86/include/asm/apicdef.h | 2 ++ arch/x86/include/asm/cpufeature.h | 1 + arch/x86/include/asm/msr-index.h | 2 ++ 3 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index 34595d5..3925d80 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -100,7 +100,9 @@ #define APIC_TIMER_BASE_CLKIN 0x0 #define APIC_TIMER_BASE_TMBASE 0x1 #define APIC_TIMER_BASE_DIV 0x2 +#define APIC_LVT_TIMER_ONESHOT (0 << 17) #define APIC_LVT_TIMER_PERIODIC (1 << 17) +#define APIC_LVT_TIMER_TSCDEADLINE (2 << 17) #define APIC_LVT_MASKED (1 << 16) #define APIC_LVT_LEVEL_TRIGGER (1 << 15) #define APIC_LVT_REMOTE_IRR (1 << 14) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 4258aac..823c4b6 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -120,6 +120,7 @@ #define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ #define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */ #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ +#define X86_FEATURE_TSC_DEADLINE_TIMER (4*32+24) /* Tsc deadline timer */ #define X86_FEATURE_AES (4*32+25) /* AES instructions */ #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ #define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index d52609a..a6962d9 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -229,6 +229,8 @@ #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_IA32_TSCDEADLINE 0x000006e0 + #define MSR_IA32_UCODE_WRITE 0x00000079 #define MSR_IA32_UCODE_REV 0x0000008b