From patchwork Thu Sep 5 14:01:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chocron, Jonathan" X-Patchwork-Id: 1158466 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=amazon.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=amazon.com header.i=@amazon.com header.b="ewKJOSDC"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46PMnq2rrFz9sP3 for ; Fri, 6 Sep 2019 00:02:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388059AbfIEOCW (ORCPT ); Thu, 5 Sep 2019 10:02:22 -0400 Received: from smtp-fw-2101.amazon.com ([72.21.196.25]:44546 "EHLO smtp-fw-2101.amazon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731733AbfIEOCV (ORCPT ); Thu, 5 Sep 2019 10:02:21 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1567692141; x=1599228141; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=QG5z1+Yu66BGKyW6lgWhjyViSH8l0CaxVJ3tSt66O5U=; b=ewKJOSDCAI9uuq3NsPbug7jalzQDG7TbklnCT6DnynZgx9bS4gWHOVfO fSEEGR1yMQ15okX25U9KwhxKOlVjk/np0BNopRiueO3bNtKc0WXGBHZhO m2HYvccfTnAgKlXMhdffLGYwo0oac558zWEN/PqEvHVzqMxJTJcRRVUvs s=; X-IronPort-AV: E=Sophos;i="5.64,470,1559520000"; d="scan'208";a="749192311" Received: from iad6-co-svc-p1-lb1-vlan2.amazon.com (HELO email-inbound-relay-1a-807d4a99.us-east-1.amazon.com) ([10.124.125.2]) by smtp-border-fw-out-2101.iad2.amazon.com with ESMTP; 05 Sep 2019 14:02:19 +0000 Received: from EX13MTAUWA001.ant.amazon.com (iad55-ws-svc-p15-lb9-vlan2.iad.amazon.com [10.40.159.162]) by email-inbound-relay-1a-807d4a99.us-east-1.amazon.com (Postfix) with ESMTPS id 5E46AA1907; Thu, 5 Sep 2019 14:02:16 +0000 (UTC) Received: from EX13D13UWA001.ant.amazon.com (10.43.160.136) by EX13MTAUWA001.ant.amazon.com (10.43.160.58) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 5 Sep 2019 14:02:15 +0000 Received: from u9ff250417f405e.ant.amazon.com (10.43.160.29) by EX13D13UWA001.ant.amazon.com (10.43.160.136) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 5 Sep 2019 14:02:09 +0000 From: Jonathan Chocron To: , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v5 7/7] PCI: dwc: Add validation that PCIe core is set to correct mode Date: Thu, 5 Sep 2019 17:01:44 +0300 Message-ID: <20190905140144.7933-3-jonnyc@amazon.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190905140018.5139-1-jonnyc@amazon.com> References: <20190905140018.5139-1-jonnyc@amazon.com> MIME-Version: 1.0 X-Originating-IP: [10.43.160.29] X-ClientProxiedBy: EX13D10UWB004.ant.amazon.com (10.43.161.121) To EX13D13UWA001.ant.amazon.com (10.43.160.136) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Some PCIe controllers can be set to either Host or EP according to some early boot FW. To make sure there is no discrepancy (e.g. FW configured the port to EP mode while the DT specifies it as a host bridge or vice versa), a check has been added for each mode. Signed-off-by: Jonathan Chocron Acked-by: Gustavo Pimentel Reviewed-by: Andrew Murray --- drivers/pci/controller/dwc/pcie-designware-ep.c | 8 ++++++++ .../pci/controller/dwc/pcie-designware-host.c | 16 ++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 65f479250087..3dd2e2697294 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -498,6 +498,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) int ret; u32 reg; void *addr; + u8 hdr_type; unsigned int nbars; unsigned int offset; struct pci_epc *epc; @@ -562,6 +563,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) if (ep->ops->ep_init) ep->ops->ep_init(ep); + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE); + if (hdr_type != PCI_HEADER_TYPE_NORMAL) { + dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n", + hdr_type); + return -EIO; + } + ret = of_property_read_u8(np, "max-functions", &epc->max_functions); if (ret < 0) epc->max_functions = 1; diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d3156446ff27..0f36a926059a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -323,6 +323,7 @@ int dw_pcie_host_init(struct pcie_port *pp) struct pci_bus *child; struct pci_host_bridge *bridge; struct resource *cfg_res; + u32 hdr_type; int ret; raw_spin_lock_init(&pci->pp.lock); @@ -464,6 +465,21 @@ int dw_pcie_host_init(struct pcie_port *pp) goto err_free_msi; } + ret = dw_pcie_rd_own_conf(pp, PCI_HEADER_TYPE, 1, &hdr_type); + if (ret != PCIBIOS_SUCCESSFUL) { + dev_err(pci->dev, "Failed reading PCI_HEADER_TYPE cfg space reg (ret: 0x%x)\n", + ret); + ret = pcibios_err_to_errno(ret); + goto err_free_msi; + } + if (hdr_type != PCI_HEADER_TYPE_BRIDGE) { + dev_err(pci->dev, + "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n", + hdr_type); + ret = -EIO; + goto err_free_msi; + } + pp->root_bus_nr = pp->busn->start; bridge->dev.parent = dev;