[RFC,1/8] Add ultravisor support in OPAL
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Message ID 20190905132919.8765-2-grimm@linux.ibm.com
State New
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Series
  • PEF support in Skiboot
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Commit Message

Ryan Grimm Sept. 5, 2019, 1:29 p.m. UTC
From: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>

Ultravisor is the firmware which runs in the new privelege mode called
ultravisor mode, which was introduced in Power 9. Ultravisor enables
running of secure virtual machines on the host.

Add routines to enable ultravisor initialisation.

Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Santosh Sivaraj <santosh@fossix.org>
---
 asm/head.S           | 22 ++++++++++++++++++++++
 include/processor.h  | 12 ++++++++++++
 include/ultravisor.h | 22 ++++++++++++++++++++++
 3 files changed, 56 insertions(+)
 create mode 100644 include/ultravisor.h

Comments

Stewart Smith Sept. 5, 2019, 4:28 p.m. UTC | #1
On Thu, Sep 5, 2019, at 6:29 AM, Ryan Grimm wrote:
> From: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
> 
> Ultravisor is the firmware which runs in the new privelege mode called
> ultravisor mode, which was introduced in Power 9. Ultravisor enables
> running of secure virtual machines on the host.

Not all P9 revisions though, right? A DD2.1 isn't going to support it.

> Add routines to enable ultravisor initialisation.

I think some information on the handover/back is needed.

is this a new entry point into skiboot? Do we call into the ultravisor and come back in a different state?

This patch itself has nothing that's used, perhaps it should be merged with another one.

> 
> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
> Signed-off-by: Santosh Sivaraj <santosh@fossix.org>
> ---
>  asm/head.S           | 22 ++++++++++++++++++++++
>  include/processor.h  | 12 ++++++++++++
>  include/ultravisor.h | 22 ++++++++++++++++++++++
>  3 files changed, 56 insertions(+)
>  create mode 100644 include/ultravisor.h
> 
> diff --git a/asm/head.S b/asm/head.S
> index e78dc520..18ce3044 100644
> --- a/asm/head.S
> +++ b/asm/head.S
> @@ -1065,3 +1065,25 @@ start_kernel_secondary:
>  	mtctr	%r3
>  	mfspr	%r3,SPR_PIR
>  	bctr
> +
> +.global start_uv
> +start_uv:
> +	mflr    %r0
> +	std     %r0,16(%r1)
> +	sync
> +	icbi    0,%r3
> +	sync
> +	isync
> +	mtctr   %r3
> +	mr      %r3,%r4
> +	LOAD_IMM64(%r8,SKIBOOT_BASE);
> +	LOAD_IMM32(%r10, opal_entry - __head)
> +	add     %r9,%r8,%r10
> +	LOAD_IMM32(%r6, EPAPR_MAGIC)
> +	addi    %r7,%r5,1
> +	li      %r4,0
> +	li      %r5,0
> +	bctrl
> +	ld      %r0,16(%r1)
> +	mtlr    %r0
> +	blr
> diff --git a/include/processor.h b/include/processor.h
> index 352fd1ec..0a552998 100644
> --- a/include/processor.h
> +++ b/include/processor.h
> @@ -11,6 +11,7 @@
>  #define MSR_HV		PPC_BIT(3)	/* Hypervisor mode */
>  #define MSR_VEC		PPC_BIT(38)	/* VMX enable */
>  #define MSR_VSX		PPC_BIT(40)	/* VSX enable */
> +#define MSR_S		PPC_BIT(41)	/* Secure Mode enable */
>  #define MSR_EE		PPC_BIT(48)	/* External Int. Enable */
>  #define MSR_PR		PPC_BIT(49)       	/* Problem state */
>  #define MSR_FP		PPC_BIT(50)	/* Floating Point Enable */
> @@ -368,6 +369,17 @@ static inline void st_le32(uint32_t *addr, uint32_t val)
>  	asm volatile("stwbrx %0,0,%1" : : "r"(val), "r"(addr), "m"(*addr));
>  }
>  
> +/*
> + * MSR bit check
> + */
> +static inline bool is_msr_bit_set(uint64_t bit)
> +{
> +	if (mfmsr() & bit)
> +		return true;
> +
> +	return false;
> +}
> +
>  #endif /* __TEST__ */
>  
>  #endif /* __ASSEMBLY__ */
> diff --git a/include/ultravisor.h b/include/ultravisor.h
> new file mode 100644
> index 00000000..9473319c
> --- /dev/null
> +++ b/include/ultravisor.h
> @@ -0,0 +1,22 @@
> +/* Copyright 2016 IBM Corp.

Was this really written entirely in 2016?

All files currently have SPDX headers, and likely so should this one.

Patch
diff mbox series

diff --git a/asm/head.S b/asm/head.S
index e78dc520..18ce3044 100644
--- a/asm/head.S
+++ b/asm/head.S
@@ -1065,3 +1065,25 @@  start_kernel_secondary:
 	mtctr	%r3
 	mfspr	%r3,SPR_PIR
 	bctr
+
+.global start_uv
+start_uv:
+	mflr    %r0
+	std     %r0,16(%r1)
+	sync
+	icbi    0,%r3
+	sync
+	isync
+	mtctr   %r3
+	mr      %r3,%r4
+	LOAD_IMM64(%r8,SKIBOOT_BASE);
+	LOAD_IMM32(%r10, opal_entry - __head)
+	add     %r9,%r8,%r10
+	LOAD_IMM32(%r6, EPAPR_MAGIC)
+	addi    %r7,%r5,1
+	li      %r4,0
+	li      %r5,0
+	bctrl
+	ld      %r0,16(%r1)
+	mtlr    %r0
+	blr
diff --git a/include/processor.h b/include/processor.h
index 352fd1ec..0a552998 100644
--- a/include/processor.h
+++ b/include/processor.h
@@ -11,6 +11,7 @@ 
 #define MSR_HV		PPC_BIT(3)	/* Hypervisor mode */
 #define MSR_VEC		PPC_BIT(38)	/* VMX enable */
 #define MSR_VSX		PPC_BIT(40)	/* VSX enable */
+#define MSR_S		PPC_BIT(41)	/* Secure Mode enable */
 #define MSR_EE		PPC_BIT(48)	/* External Int. Enable */
 #define MSR_PR		PPC_BIT(49)       	/* Problem state */
 #define MSR_FP		PPC_BIT(50)	/* Floating Point Enable */
@@ -368,6 +369,17 @@  static inline void st_le32(uint32_t *addr, uint32_t val)
 	asm volatile("stwbrx %0,0,%1" : : "r"(val), "r"(addr), "m"(*addr));
 }
 
+/*
+ * MSR bit check
+ */
+static inline bool is_msr_bit_set(uint64_t bit)
+{
+	if (mfmsr() & bit)
+		return true;
+
+	return false;
+}
+
 #endif /* __TEST__ */
 
 #endif /* __ASSEMBLY__ */
diff --git a/include/ultravisor.h b/include/ultravisor.h
new file mode 100644
index 00000000..9473319c
--- /dev/null
+++ b/include/ultravisor.h
@@ -0,0 +1,22 @@ 
+/* Copyright 2016 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *	http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ULTRAVISOR_H
+#define __ULTRAVISOR_H
+
+extern int start_uv(uint64_t entry, void *ptr);
+
+#endif /* __ULTRAVISOR_H */