From patchwork Thu Sep 5 10:45:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1158358 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="P6Blh38U"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46PHRz2CvYz9sP3 for ; Thu, 5 Sep 2019 20:46:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388128AbfIEKqe (ORCPT ); Thu, 5 Sep 2019 06:46:34 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17827 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727900AbfIEKqe (ORCPT ); Thu, 5 Sep 2019 06:46:34 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 05 Sep 2019 03:46:36 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 05 Sep 2019 03:46:33 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 05 Sep 2019 03:46:33 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 5 Sep 2019 10:46:32 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 5 Sep 2019 10:46:32 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 05 Sep 2019 03:46:32 -0700 From: Vidya Sagar To: , , , , , CC: , , , , , , , , , , , , Subject: [PATCH V4 5/6] arm64: tegra: Add configuration for PCIe C5 sideband signals Date: Thu, 5 Sep 2019 16:15:52 +0530 Message-ID: <20190905104553.2884-6-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190905104553.2884-1-vidyas@nvidia.com> References: <20190905104553.2884-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1567680396; bh=DAtKaIQsQsPA5EiUN0jYyuLZMRcf1ZUk/rDuDsND/+4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=P6Blh38UUgfUFC+hIME1XcvB0wlcRrDbPP0rkDF91LM6sJb3fE26PF2sscpZ/mbqX DllNDRgkCSn8XygobD3ledvbg5bkTVlo8V81aHzIaaTPpA1rgYNMg7CtFpopQjMlFw G1sPcq6EJpjqvQQyPi6DK5nTFCK5LRFHR5O2CTkVCNAdiktzNuSo3/p5sS5CH8Ugb2 WoK+nEMyGN9u4tAQzMJM6VaSaVvP1mnxjcx5Dk1xL79KaCYr/5Fy0zhmENtHwsgqQm 6uKojMYAc8JCGdLcopjAbHh8SBTsB0dhKQxwGZL1fZNblnXvO1dwzWGb4G03K5U5DE 8L3xdZh+3bzkA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add support to configure PCIe C5's sideband signals PERST# and CLKREQ# as output and bi-directional signals respectively which unlike other PCIe controllers sideband signals are not configured by default. Signed-off-by: Vidya Sagar Reviewed-by: Andrew Murray --- V4: * None V3: * None V2: * None arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 +++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index adebbbf36bd0..3c0cf54f0aab 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -3,8 +3,9 @@ #include #include #include -#include +#include #include +#include #include / { @@ -130,6 +131,38 @@ }; }; + pinmux: pinmux@2430000 { + compatible = "nvidia,tegra194-pinmux"; + reg = <0x2430000 0x17000 + 0xc300000 0x4000>; + + status = "okay"; + + pex_rst_c5_out_state: pex_rst_c5_out { + pex_rst { + nvidia,pins = "pex_l5_rst_n_pgg1"; + nvidia,schmitt = ; + nvidia,lpdr = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,tristate = ; + nvidia,pull = ; + }; + }; + + clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { + clkreq { + nvidia,pins = "pex_l5_clkreq_n_pgg0"; + nvidia,schmitt = ; + nvidia,lpdr = ; + nvidia,enable-input = ; + nvidia,io-high-voltage = ; + nvidia,tristate = ; + nvidia,pull = ; + }; + }; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x40>; @@ -1365,6 +1398,9 @@ num-viewport = <8>; linux,pci-domain = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; clock-names = "core", "core_m";