[v3,1/2] dt-bindings: phy: intel-sdxc-phy: Add YAML schema for LGM SDXC PHY
diff mbox series

Message ID 20190904062719.37462-1-vadivel.muruganx.ramuthevar@linux.intel.com
State Changes Requested
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  • [v3,1/2] dt-bindings: phy: intel-sdxc-phy: Add YAML schema for LGM SDXC PHY
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robh/dt-meta-schema fail build log
robh/checkpatch warning "total: 0 errors, 1 warnings, 69 lines checked"

Commit Message

Ramuthevar, Vadivel MuruganX Sept. 4, 2019, 6:27 a.m. UTC
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>

Add a YAML schema to use the host controller driver with the
SDXC PHY on Intel's Lightning Mountain SoC.

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
 changes in v3:
   - Rob's review comments addressed and updated the patch
   - merged syscon and sdxc yaml file as single file after discussion

 changes in v2:
   - As per Rob's review comment syscon node entry added instead of reference
   - splitted two patches one for syscon and another for sdxc phy
---
 .../bindings/phy/intel,lgm-sdxc-phy.yaml           | 69 ++++++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml

Comments

Andy Shevchenko Sept. 4, 2019, 12:39 p.m. UTC | #1
On Wed, Sep 04, 2019 at 02:27:19PM +0800, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> 
> Add support for SDXC PHY on Intel's Lightning Mountain SoC.

What's the difference to eMMC PHY?
Can they share the same / similar code?
Ramuthevar, Vadivel MuruganX Sept. 4, 2019, 1:38 p.m. UTC | #2
Hi Andy,

  Thank you for the review comments .

On 4/9/2019 8:39 PM, Andy Shevchenko wrote:
> On Wed, Sep 04, 2019 at 02:27:19PM +0800, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>>
>> Add support for SDXC PHY on Intel's Lightning Mountain SoC.
> What's the difference to eMMC PHY?
> Can they share the same / similar code?
eMMC and SDXC interface controller share the common driver since IP block
of the vendor(SDHC-ARASAN) is same, where as PHY is different. The PHY 
is designed by Intel itself to support
specific eMMC card and SD/SDIO card specific. e.g: PAD, CLK, driver 
strength..etc.

IP block of the PHY  is different module for eMMC and SDXC to adapt the 
controllers, that is reason we have different drivers.
---
With Best Regards
Vadivel
Rob Herring Sept. 17, 2019, 8:24 p.m. UTC | #3
On Wed, Sep 04, 2019 at 02:27:18PM +0800, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> 
> Add a YAML schema to use the host controller driver with the
> SDXC PHY on Intel's Lightning Mountain SoC.

Same issues on this one as emmc phy.

> 
> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> ---
>  changes in v3:
>    - Rob's review comments addressed and updated the patch
>    - merged syscon and sdxc yaml file as single file after discussion
> 
>  changes in v2:
>    - As per Rob's review comment syscon node entry added instead of reference
>    - splitted two patches one for syscon and another for sdxc phy
> ---
>  .../bindings/phy/intel,lgm-sdxc-phy.yaml           | 69 ++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml
Ramuthevar, Vadivel MuruganX Sept. 18, 2019, 2:26 a.m. UTC | #4
Hi Rob,

     Thank you for the review comments.

On 18/9/2019 4:24 AM, Rob Herring wrote:
> On Wed, Sep 04, 2019 at 02:27:18PM +0800, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>>
>> Add a YAML schema to use the host controller driver with the
>> SDXC PHY on Intel's Lightning Mountain SoC.
> Same issues on this one as emmc phy.

Agreed!, once clarified the emmc phy comments, let me update further. 
Thanks!

Best Regards
Vadivel
>> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>> ---
>>   changes in v3:
>>     - Rob's review comments addressed and updated the patch
>>     - merged syscon and sdxc yaml file as single file after discussion
>>
>>   changes in v2:
>>     - As per Rob's review comment syscon node entry added instead of reference
>>     - splitted two patches one for syscon and another for sdxc phy
>> ---
>>   .../bindings/phy/intel,lgm-sdxc-phy.yaml           | 69 ++++++++++++++++++++++
>>   1 file changed, 69 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml
new file mode 100644
index 000000000000..dfdedcf10f3f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml
@@ -0,0 +1,69 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/intel,lgm-sdxc-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Lightning Mountain(LGM) SDXC PHY Device Tree Bindings
+
+maintainers:
+  - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
+
+description: Bindings for SDXC PHY on Intel's Lightning Mountain SoC, syscon
+  node is used to reference the base address of SDXC phy registers.
+
+select:
+  properties:
+    compatible:
+      contains:
+        const: intel,lgm-syscon
+
+    reg:
+      maxItems: 1
+
+  required:
+    - compatible
+    - reg
+
+properties:
+  "#phy-cells":
+    const: 0
+
+  compatible:
+    contains:
+      const: intel,lgm-sdxc-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    maxItems: 1
+
+required:
+  - "#phy-cells"
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+
+examples:
+  - |
+    sysconf: chiptop@e0200000 {
+      compatible = "intel,lgm-syscon";
+      reg = <0xe0200000 0x100>;
+
+      sdxc-phy: sdxc-phy {
+        compatible = "intel,lgm-sdxc-phy";
+        reg = <0x0080 0x4>,
+              <0x0084 0x4>,
+              <0x0088 0x4>,
+              <0x008c 0x4>;
+        clocks = <&sdxc>;
+        clock-names = "sdxcclk";
+        #phy-cells = <0>;
+      };
+    };
+...