From patchwork Tue Sep 3 17:04:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1157195 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46NDqM2qnjz9sBF for ; Wed, 4 Sep 2019 03:44:47 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46NDqM1gGyzDqsj for ; Wed, 4 Sep 2019 03:44:47 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=kaod.org (client-ip=178.32.119.250; helo=2.mo1.mail-out.ovh.net; envelope-from=clg@kaod.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kaod.org X-Greylist: delayed 2334 seconds by postgrey-1.36 at bilbo; Wed, 04 Sep 2019 03:44:40 AEST Received: from 2.mo1.mail-out.ovh.net (2.mo1.mail-out.ovh.net [178.32.119.250]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46NDqD5GB4zDqp5 for ; Wed, 4 Sep 2019 03:44:39 +1000 (AEST) Received: from player779.ha.ovh.net (unknown [10.108.35.197]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 23B8618D5B3 for ; Tue, 3 Sep 2019 19:05:41 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player779.ha.ovh.net (Postfix) with ESMTPSA id 5FC7E94D02AB; Tue, 3 Sep 2019 17:05:37 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: skiboot@lists.ozlabs.org Date: Tue, 3 Sep 2019 19:04:13 +0200 Message-Id: <20190903170413.4373-23-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190903170413.4373-1-clg@kaod.org> References: <20190903170413.4373-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 11341471239346359257 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrudejfedgjeelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm Subject: [Skiboot] [PATCH 22/22] xive/p9: rework IRQ number encoding X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Remove emulation mode from IRQ number encoding to have a 24 bit IRQ number space. We still keep a maximum of 1M per chip for the moment but it can now be increased to 16M if needed. Signed-off-by: Cédric Le Goater --- hw/xive-p9.c | 37 +++++++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/hw/xive-p9.c b/hw/xive-p9.c index 90d259adcbba..a1a0c24fc7e2 100644 --- a/hw/xive-p9.c +++ b/hw/xive-p9.c @@ -139,8 +139,9 @@ * we will simply share it and ensure we don't hand out IPIs that * overlap the HW interrupts. */ -#define MAX_INT_ENTRIES (1 * 1024 * 1024) +#define XIVE_INT_ORDER 20 #define XIVE_INT_FIRST 0x10 +#define MAX_INT_ENTRIES (1 << XIVE_INT_ORDER) /* Corresponding direct table sizes */ #define SBE_SIZE (MAX_INT_ENTRIES / 4) @@ -156,7 +157,8 @@ * * XXX Adjust that based on BAR value ? */ -#define MAX_EQ_COUNT (1 * 1024 * 1024) +#define XIVE_END_ORDER 20 +#define MAX_EQ_COUNT (1 << XIVE_END_ORDER) #define EQ_PER_PAGE (0x10000 / 32) // Use sizeof ? #define IND_EQ_TABLE_SIZE ((MAX_EQ_COUNT / EQ_PER_PAGE) * 8) @@ -376,24 +378,35 @@ static uint32_t xive_chip_to_block(uint32_t chip_id) /* Conversion between GIRQ and block/index. * * ------------------------------------ - * |0000000E|BLOC| INDEX| + * |000E|BLOC| INDEX| * ------------------------------------ - * 8 4 20 + * 4 4 24 * * the E bit indicates that this is an escalation interrupt, in * that case, the BLOC/INDEX represents the EQ containig the * corresponding escalation descriptor. * * Global interrupt numbers for non-escalation interrupts are thus - * limited to 24 bits which is necessary for our XICS emulation since - * the top 8 bits are reserved for the CPPR value. - * + * limited to 28 bits. */ -#define GIRQ_TO_BLK(__g) (((__g) >> 20) & 0xf) -#define GIRQ_TO_IDX(__g) ((__g) & 0x000fffff) -#define BLKIDX_TO_GIRQ(__b,__i) (((uint32_t)(__b)) << 20 | (__i)) -#define GIRQ_IS_ESCALATION(__g) ((__g) & 0x01000000) -#define MAKE_ESCALATION_GIRQ(__b,__i)(BLKIDX_TO_GIRQ(__b,__i) | 0x01000000) + +#define INT_SHIFT 24 +#define INT_ESC_SHIFT 28 + +#if XIVE_INT_ORDER > INT_SHIFT +#error "Too many ESBs for IRQ encoding" +#endif + +#if XIVE_END_ORDER > INT_SHIFT +#error "Too many ENDs for escalation IRQ number encoding" +#endif + +#define GIRQ_TO_BLK(__g) (((__g) >> INT_SHIFT) & 0xf) +#define GIRQ_TO_IDX(__g) ((__g) & ((1 << INT_SHIFT) - 1)) +#define BLKIDX_TO_GIRQ(__b,__i) (((uint32_t)(__b)) << INT_SHIFT | (__i)) + +#define GIRQ_IS_ESCALATION(__g) ((__g) & (1 << INT_ESC_SHIFT)) +#define MAKE_ESCALATION_GIRQ(__b,__i)(BLKIDX_TO_GIRQ(__b,__i) | (1 << INT_ESC_SHIFT)) /* Block/IRQ to chip# conversions */ #define PC_BLK_TO_CHIP(__b) (xive_block_to_chip[__b])