[22/22] xive/p9: rework IRQ number encoding
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Message ID 20190903170413.4373-23-clg@kaod.org
State New
Headers show
Series
  • xive: new interfaces, fixes and cleanups in a new driver
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Commit Message

Cédric Le Goater Sept. 3, 2019, 5:04 p.m. UTC
Remove emulation mode from IRQ number encoding to have a 24 bit IRQ
number space. We still keep a maximum of 1M per chip for the moment
but it can now be increased to 16M if needed.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/xive-p9.c | 37 +++++++++++++++++++++++++------------
 1 file changed, 25 insertions(+), 12 deletions(-)

Patch
diff mbox series

diff --git a/hw/xive-p9.c b/hw/xive-p9.c
index 90d259adcbba..a1a0c24fc7e2 100644
--- a/hw/xive-p9.c
+++ b/hw/xive-p9.c
@@ -139,8 +139,9 @@ 
  * we will simply share it and ensure we don't hand out IPIs that
  * overlap the HW interrupts.
  */
-#define MAX_INT_ENTRIES		(1 * 1024 * 1024)
+#define XIVE_INT_ORDER		20
 #define XIVE_INT_FIRST		0x10
+#define MAX_INT_ENTRIES		(1 << XIVE_INT_ORDER)
 
 /* Corresponding direct table sizes */
 #define SBE_SIZE	(MAX_INT_ENTRIES / 4)
@@ -156,7 +157,8 @@ 
  *
  * XXX Adjust that based on BAR value ?
  */
-#define MAX_EQ_COUNT		(1 * 1024 * 1024)
+#define XIVE_END_ORDER		20
+#define MAX_EQ_COUNT		(1 << XIVE_END_ORDER)
 #define EQ_PER_PAGE		(0x10000 / 32) // Use sizeof ?
 #define IND_EQ_TABLE_SIZE	((MAX_EQ_COUNT / EQ_PER_PAGE) * 8)
 
@@ -376,24 +378,35 @@  static uint32_t xive_chip_to_block(uint32_t chip_id)
 /* Conversion between GIRQ and block/index.
  *
  * ------------------------------------
- * |0000000E|BLOC|               INDEX|
+ * |000E|BLOC|                   INDEX|
  * ------------------------------------
- *      8      4           20
+ *   4     4           24
  *
  * the E bit indicates that this is an escalation interrupt, in
  * that case, the BLOC/INDEX represents the EQ containig the
  * corresponding escalation descriptor.
  *
  * Global interrupt numbers for non-escalation interrupts are thus
- * limited to 24 bits which is necessary for our XICS emulation since
- * the top 8 bits are reserved for the CPPR value.
- *
+ * limited to 28 bits.
  */
-#define GIRQ_TO_BLK(__g)	(((__g) >> 20) & 0xf)
-#define GIRQ_TO_IDX(__g)	((__g) & 0x000fffff)
-#define BLKIDX_TO_GIRQ(__b,__i)	(((uint32_t)(__b)) << 20 | (__i))
-#define GIRQ_IS_ESCALATION(__g)	((__g) & 0x01000000)
-#define MAKE_ESCALATION_GIRQ(__b,__i)(BLKIDX_TO_GIRQ(__b,__i) | 0x01000000)
+
+#define INT_SHIFT		24
+#define INT_ESC_SHIFT		28
+
+#if XIVE_INT_ORDER > INT_SHIFT
+#error "Too many ESBs for IRQ encoding"
+#endif
+
+#if XIVE_END_ORDER > INT_SHIFT
+#error "Too many ENDs for escalation IRQ number encoding"
+#endif
+
+#define GIRQ_TO_BLK(__g)	(((__g) >> INT_SHIFT) & 0xf)
+#define GIRQ_TO_IDX(__g)	((__g) & ((1 << INT_SHIFT) - 1))
+#define BLKIDX_TO_GIRQ(__b,__i)	(((uint32_t)(__b)) << INT_SHIFT | (__i))
+
+#define GIRQ_IS_ESCALATION(__g)	((__g) & (1 << INT_ESC_SHIFT))
+#define MAKE_ESCALATION_GIRQ(__b,__i)(BLKIDX_TO_GIRQ(__b,__i) | (1 << INT_ESC_SHIFT))
 
 /* Block/IRQ to chip# conversions */
 #define PC_BLK_TO_CHIP(__b)	(xive_block_to_chip[__b])