[10/22] xive/p9: obsolete OPAL_XIVE_IRQ_SHIFT_BUG flags
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Message ID 20190903170413.4373-11-clg@kaod.org
State New
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Series
  • xive: new interfaces, fixes and cleanups in a new driver
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Commit Message

Cédric Le Goater Sept. 3, 2019, 5:04 p.m. UTC
These were needed to workaround HW bugs in PHB4 LSIs of POWER9 DD1.0
processors.

HW395455 P9/PHB4: Wrong Interrupt ESB CI Load Opcode Location in 64K
page mode

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/opal-api.h | 2 +-
 include/xive.h     | 2 +-
 hw/phb4.c          | 1 +
 hw/xive-p9.c       | 7 -------
 4 files changed, 3 insertions(+), 9 deletions(-)

Patch
diff mbox series

diff --git a/include/opal-api.h b/include/opal-api.h
index 2ceb832e489f..bd69618d90fc 100644
--- a/include/opal-api.h
+++ b/include/opal-api.h
@@ -1148,7 +1148,7 @@  enum {
 	OPAL_XIVE_IRQ_TRIGGER_PAGE	= 0x00000001,
 	OPAL_XIVE_IRQ_STORE_EOI		= 0x00000002,
 	OPAL_XIVE_IRQ_LSI		= 0x00000004,
-	OPAL_XIVE_IRQ_SHIFT_BUG		= 0x00000008,
+	OPAL_XIVE_IRQ_SHIFT_BUG		= 0x00000008, /* DD1.0 workaround */
 	OPAL_XIVE_IRQ_MASK_VIA_FW	= 0x00000010, /* DD1.0 workaround */
 	OPAL_XIVE_IRQ_EOI_VIA_FW	= 0x00000020, /* DD1.0 workaround */
 };
diff --git a/include/xive.h b/include/xive.h
index 27dbaee6df5f..cae3a1b343de 100644
--- a/include/xive.h
+++ b/include/xive.h
@@ -36,7 +36,7 @@  uint32_t xive_get_notify_base(uint32_t girq);
 #define XIVE_SRC_EOI_PAGE1	0x02 /* EOI on the second page */
 #define XIVE_SRC_STORE_EOI	0x04 /* EOI using stores supported */
 #define XIVE_SRC_LSI		0x08 /* Interrupt is an LSI */
-#define XIVE_SRC_SHIFT_BUG	0x10 /* ESB update offset << 4 */
+#define XIVE_SRC_SHIFT_BUG	0x10 /* ESB update offset << 4 (PHB4 LSI DD1) */
 
 struct irq_source_ops;
 void xive_register_hw_source(uint32_t base, uint32_t count, uint32_t shift,
diff --git a/hw/phb4.c b/hw/phb4.c
index 3c71427aef2f..f02e675f0a02 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -5738,6 +5738,7 @@  static void phb4_create(struct dt_node *np)
 	xive_register_hw_source(p->base_msi, p->num_irqs - 8, 16,
 				p->int_mmio, irq_flags, NULL, NULL);
 
+	/* XIVE_SRC_SHIFT_BUG is a DD1 workaround */
 	xive_register_hw_source(p->base_lsi, 8, 16,
 				p->int_mmio + ((p->num_irqs - 8) << 16),
 				XIVE_SRC_LSI | XIVE_SRC_SHIFT_BUG,
diff --git a/hw/xive-p9.c b/hw/xive-p9.c
index 4038f6ea9950..2232220babd6 100644
--- a/hw/xive-p9.c
+++ b/hw/xive-p9.c
@@ -2238,9 +2238,6 @@  static void xive_update_irq_mask(struct xive_src *s, uint32_t idx, bool masked)
 	else
 		offset = 0xc00; /* PQ = 00 */
 
-	if (s->flags & XIVE_SRC_SHIFT_BUG)
-		offset <<= 4;
-
 	in_be64(mmio_base + offset);
 }
 
@@ -2423,8 +2420,6 @@  static void __xive_source_eoi(struct irq_source *is, uint32_t isn)
 			in_be64(mmio_base);
 		else {
 			offset = 0xc00;
-			if (s->flags & XIVE_SRC_SHIFT_BUG)
-				offset <<= 4;
 			eoi_val = in_be64(mmio_base + offset);
 			xive_vdbg(s->xive, "ISN: %08x EOI=%llx\n",
 				  isn, eoi_val);
@@ -3616,8 +3611,6 @@  static uint64_t xive_convert_irq_flags(uint64_t iflags)
 
 	if (iflags & XIVE_SRC_LSI)
 		oflags |= OPAL_XIVE_IRQ_LSI;
-	if (iflags & XIVE_SRC_SHIFT_BUG)
-		oflags |= OPAL_XIVE_IRQ_SHIFT_BUG;
 	return oflags;
 }