[18/22] xive/p9: introduce the ESB magic MMIO offsets
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Message ID 20190903170413.4373-19-clg@kaod.org
State New
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Series
  • xive: new interfaces, fixes and cleanups in a new driver
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Commit Message

Cédric Le Goater Sept. 3, 2019, 5:04 p.m. UTC
The following offsets into the ESB MMIO allow to read or manipulate
the PQ bits. They must be used with an 8-byte load instruction. They
all return the previous state of the interrupt (atomically).

Additionally, some ESB pages support doing an EOI via a store and
some ESBs support doing a trigger via a separate trigger page.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/xive-regs.h | 18 ++++++++++++++++++
 hw/xive-p9.c        | 14 +++++++-------
 2 files changed, 25 insertions(+), 7 deletions(-)

Patch
diff mbox series

diff --git a/include/xive-regs.h b/include/xive-regs.h
index f7d9fd4e0a3e..e395e9ab702b 100644
--- a/include/xive-regs.h
+++ b/include/xive-regs.h
@@ -94,4 +94,22 @@ 
 #define TM_QW3_NSR_I		PPC_BIT8(2)
 #define TM_QW3_NSR_GRP_LVL	PPC_BIT8(3,7)
 
+/*
+ * "magic" Event State Buffer (ESB) MMIO offsets.
+ *
+ * The following offsets into the ESB MMIO allow to read or manipulate
+ * the PQ bits. They must be used with an 8-byte load instruction.
+ * They all return the previous state of the interrupt (atomically).
+ *
+ * Additionally, some ESB pages support doing an EOI via a store and
+ * some ESBs support doing a trigger via a separate trigger page.
+ */
+#define XIVE_ESB_STORE_EOI      0x400 /* Store */
+#define XIVE_ESB_LOAD_EOI       0x000 /* Load */
+#define XIVE_ESB_GET            0x800 /* Load */
+#define XIVE_ESB_SET_PQ_00      0xc00 /* Load */
+#define XIVE_ESB_SET_PQ_01      0xd00 /* Load */
+#define XIVE_ESB_SET_PQ_10      0xe00 /* Load */
+#define XIVE_ESB_SET_PQ_11      0xf00 /* Load */
+
 #endif /* XIVE_REGS_H__ */
diff --git a/hw/xive-p9.c b/hw/xive-p9.c
index 1c4cd400bb3d..cdc44a123b08 100644
--- a/hw/xive-p9.c
+++ b/hw/xive-p9.c
@@ -1082,7 +1082,7 @@  static void xive_scrub_workaround_eq(struct xive *x, uint32_t block __unused, ui
 	/* Ensure the above has returned before we do anything else
 	 * the XIVE store queue is completely empty
 	 */
-	load_wait(in_be64(mmio + 0x800));
+	load_wait(in_be64(mmio + XIVE_ESB_GET));
 }
 
 static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype,
@@ -2237,9 +2237,9 @@  static void xive_update_irq_mask(struct xive_src *s, uint32_t idx, bool masked)
 	if (s->flags & XIVE_SRC_EOI_PAGE1)
 		mmio_base += 1ull << (s->esb_shift - 1);
 	if (masked)
-		offset = 0xd00; /* PQ = 01 */
+		offset = XIVE_ESB_SET_PQ_01;
 	else
-		offset = 0xc00; /* PQ = 00 */
+		offset = XIVE_ESB_SET_PQ_00;
 
 	in_be64(mmio_base + offset);
 }
@@ -2252,7 +2252,7 @@  static int64_t xive_sync(struct xive *x)
 	lock(&x->lock);
 
 	/* Second 2K range of second page */
-	p = x->ic_base + (1 << x->ic_shift) + 0x800;
+	p = x->ic_base + (1 << x->ic_shift) + XIVE_ESB_GET;
 
 	/* TODO: Make this more fine grained */
 	out_be64(p + (10 << 7), 0); /* Sync OS escalations */
@@ -2405,7 +2405,7 @@  static void __xive_source_eoi(struct irq_source *is, uint32_t isn)
 
 	/* If the XIVE supports the new "store EOI facility, use it */
 	if (s->flags & XIVE_SRC_STORE_EOI)
-		out_be64(mmio_base + 0x400, 0);
+		out_be64(mmio_base + XIVE_ESB_STORE_EOI, 0);
 	else {
 		uint64_t offset;
 
@@ -2422,7 +2422,7 @@  static void __xive_source_eoi(struct irq_source *is, uint32_t isn)
 		if (s->flags & XIVE_SRC_LSI)
 			in_be64(mmio_base);
 		else {
-			offset = 0xc00;
+			offset = XIVE_ESB_SET_PQ_00;
 			eoi_val = in_be64(mmio_base + offset);
 			xive_vdbg(s->xive, "ISN: %08x EOI=%llx\n",
 				  isn, eoi_val);
@@ -3260,7 +3260,7 @@  static int64_t opal_xive_eoi(uint32_t xirr)
 		 * Note: We aren't doing an actual EOI. Instead we are clearing
 		 * both P and Q and will re-check the queue if Q was set.
 		 */
-		eoi_val = in_8(xs->eqmmio + 0xc00);
+		eoi_val = in_8(xs->eqmmio + XIVE_ESB_SET_PQ_00);
 		xive_cpu_vdbg(c, "  isn %08x, eoi_val=%02x\n", xirr, eoi_val);
 
 		/* Q was set ? Check EQ again after doing a sync to ensure