[21/22] xive/p9: remove XICS emulation OPAL calls
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Message ID 20190903170413.4373-22-clg@kaod.org
State New
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Series
  • xive: new interfaces, fixes and cleanups in a new driver
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Commit Message

Cédric Le Goater Sept. 3, 2019, 5:04 p.m. UTC
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/xive-p9.c | 117 +--------------------------------------------------
 1 file changed, 1 insertion(+), 116 deletions(-)

Patch
diff mbox series

diff --git a/hw/xive-p9.c b/hw/xive-p9.c
index c66f4ef08f2c..90d259adcbba 100644
--- a/hw/xive-p9.c
+++ b/hw/xive-p9.c
@@ -2064,19 +2064,6 @@  static int64_t xive_set_irq_targetting(uint32_t isn, uint32_t target,
 	return rc;
 }
 
-static int64_t xive_source_get_xive(struct irq_source *is __unused,
-				    uint32_t isn, uint16_t *server,
-				    uint8_t *prio)
-{
-	uint32_t target_id;
-
-	if (xive_get_irq_targetting(isn, &target_id, prio, NULL)) {
-		*server = target_id << 2;
-		return OPAL_SUCCESS;
-	} else
-		return OPAL_PARAMETER;
-}
-
 static void xive_update_irq_mask(struct xive_src *s, uint32_t idx, bool masked)
 {
 	void *mmio_base = s->esb_mmio + (1ul << s->esb_shift) * idx;
@@ -2160,12 +2147,7 @@  static int64_t __xive_set_irq_config(struct irq_source *is, uint32_t girq,
 	/* Do we need to update the mask ? */
 	if (old_prio != prio && (old_prio == 0xff || prio == 0xff)) {
 		/* The source has special variants of masking/unmasking */
-		if (s->orig_ops && s->orig_ops->set_xive) {
-			/* We don't pass as server on source ops ! Targetting
-			 * is handled by the XIVE
-			 */
-			rc = s->orig_ops->set_xive(is, girq, 0, prio);
-		} else if (update_esb) {
+		if (update_esb) {
 			/* Ensure it's enabled/disabled in the source
 			 * controller
 			 */
@@ -2202,100 +2184,6 @@  static int64_t xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
 	return __xive_set_irq_config(is, girq, vp, prio, lirq, update_esb,
 				     true);
 }
-
-static int64_t xive_source_set_xive(struct irq_source *is,
-				    uint32_t isn, uint16_t server, uint8_t prio)
-{
-	/*
-	 * WARNING: There is an inherent race with the use of the
-	 * mask bit in the EAS/IVT. When masked, interrupts are "lost"
-	 * but their P/Q bits are still set. So when unmasking, one has
-	 * to check the P bit and possibly trigger a resend.
-	 *
-	 * We "deal" with it by relying on the fact that the OS will
-	 * lazy disable MSIs. Thus mask will only be called if the
-	 * interrupt occurred while already logically masked. Thus
-	 * losing subsequent occurrences is of no consequences, we just
-	 * need to "cleanup" P and Q when unmasking.
-	 *
-	 * This needs to be documented in the OPAL APIs
-	 */
-
-	/* Unmangle server */
-	server >>= 2;
-
-	/* Set logical irq to match isn */
-	return __xive_set_irq_config(is, isn, server, prio, isn, true, true);
-}
-
-static void __xive_source_eoi(struct irq_source *is, uint32_t isn)
-{
-	struct xive_src *s = container_of(is, struct xive_src, is);
-	uint32_t idx = isn - s->esb_base;
-	struct xive_ive *ive;
-	void *mmio_base;
-	uint64_t eoi_val;
-
-	/* Grab the IVE */
-	ive = s->xive->ivt_base;
-	if (!ive)
-		return;
-	ive += GIRQ_TO_IDX(isn);
-
-	/* XXX To fix the races with mask/unmask potentially causing
-	 * multiple queue entries, we need to keep track of EOIs here,
-	 * before the masked test below
-	 */
-
-	/* If it's invalid or masked, don't do anything */
-	if ((ive->w & IVE_MASKED) || !(ive->w & IVE_VALID))
-		return;
-
-	/* Grab MMIO control address for that ESB */
-	mmio_base = s->esb_mmio + (1ull << s->esb_shift) * idx;
-
-	/* If the XIVE supports the new "store EOI facility, use it */
-	if (s->flags & XIVE_SRC_STORE_EOI)
-		out_be64(mmio_base + XIVE_ESB_STORE_EOI, 0);
-	else {
-		uint64_t offset;
-
-		/* Otherwise for EOI, we use the special MMIO that does
-		 * a clear of both P and Q and returns the old Q.
-		 *
-		 * This allows us to then do a re-trigger if Q was set
-		 * rather than synthetizing an interrupt in software
-		 */
-		if (s->flags & XIVE_SRC_EOI_PAGE1)
-			mmio_base += 1ull << (s->esb_shift - 1);
-
-		/* LSIs don't need anything special, just EOI */
-		if (s->flags & XIVE_SRC_LSI)
-			in_be64(mmio_base);
-		else {
-			offset = XIVE_ESB_SET_PQ_00;
-			eoi_val = in_be64(mmio_base + offset);
-			xive_vdbg(s->xive, "ISN: %08x EOI=%llx\n",
-				  isn, eoi_val);
-			if (!(eoi_val & 1))
-				return;
-
-			/* Re-trigger always on page0 or page1 ? */
-			out_be64(mmio_base, 0);
-		}
-	}
-}
-
-static void xive_source_eoi(struct irq_source *is, uint32_t isn)
-{
-	struct xive_src *s = container_of(is, struct xive_src, is);
-
-	if (s->orig_ops && s->orig_ops->eoi)
-		s->orig_ops->eoi(is, isn);
-	else
-		__xive_source_eoi(is, isn);
-}
-
 static void xive_source_interrupt(struct irq_source *is, uint32_t isn)
 {
 	struct xive_src *s = container_of(is, struct xive_src, is);
@@ -2324,9 +2212,6 @@  static char *xive_source_name(struct irq_source *is, uint32_t isn)
 }
 
 static const struct irq_source_ops xive_irq_source_ops = {
-	.get_xive = xive_source_get_xive,
-	.set_xive = xive_source_set_xive,
-	.eoi = xive_source_eoi,
 	.interrupt = xive_source_interrupt,
 	.attributes = xive_source_attributes,
 	.name = xive_source_name,