[ARM] Cleanup highpart multiply patterns

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Series	[ARM] Cleanup highpart multiply patterns \| expand [ARM] Cleanup highpart multiply patterns

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From: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
To: GCC Patches <gcc-patches@gcc.gnu.org>,
	Kyrylo Tkachov	<Kyrylo.Tkachov@arm.com>,
	Richard Earnshaw <Richard.Earnshaw@arm.com>
CC: nd <nd@arm.com>
Subject: [PATCH][ARM] Cleanup highpart multiply patterns
Date: Tue, 3 Sep 2019 15:39:58 +0000
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Series

[ARM] Cleanup highpart multiply patterns | expand

Commit Message

Wilco Dijkstra Sept. 3, 2019, 3:39 p.m. UTC

Cleanup the various highpart multiply patterns using iterators.
As a result the signed and unsigned variants and the pre-Armv6
multiply operand constraints are all handled in a single pattern
and simple expander.

Bootstrap OK on armhf, regress passes.

ChangeLog:
2019-09-03  Wilco Dijkstra  <wdijkstr@arm.com>

	* config/arm/arm.md (smulsi3_highpart): Use <US> and <SE> iterators.
	(smulsi3_highpart_nov6): Remove pattern.
	(smulsi3_highpart_v6): Likewise.
	(umulsi3_highpart): Likewise.
	(umulsi3_highpart_nov6): Likewise.
	(umulsi3_highpart_v6): Likewise.
	(<US>mull_high): Add new combined multiply pattern.
--

Comments

Wilco Dijkstra Sept. 9, 2019, 5:07 p.m. UTC | #1

ping
   
 
Cleanup the various highpart multiply patterns using iterators.
 As a result the signed and unsigned variants and the pre-Armv6
 multiply operand constraints are all handled in a single pattern
 and simple expander.
 
 Bootstrap OK on armhf, regress passes.
 
 ChangeLog:
 2019-09-03  Wilco Dijkstra  <wdijkstr@arm.com>
 
         * config/arm/arm.md (smulsi3_highpart): Use <US> and <SE> iterators.
         (smulsi3_highpart_nov6): Remove pattern.
         (smulsi3_highpart_v6): Likewise.
         (umulsi3_highpart): Likewise.
         (umulsi3_highpart_nov6): Likewise.
         (umulsi3_highpart_v6): Likewise.
         (<US>mull_high): Add new combined multiply pattern.
 --
 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
 index 681358512e88f6823d1b6d59038f387daaec226e..1ab203810bf143927a8afa0d00d82537cd7c75ed 100644
 --- a/gcc/config/arm/arm.md
 +++ b/gcc/config/arm/arm.md
 @@ -1776,92 +1776,34 @@ (define_insn "*umulsidi3adddi_v6"
     (set_attr "predicable" "yes")]
  )
  
 -(define_expand "smulsi3_highpart"
 +(define_expand "<US>mulsi3_highpart"
    [(parallel
      [(set (match_operand:SI 0 "s_register_operand")
            (truncate:SI
             (lshiftrt:DI
              (mult:DI
 -            (sign_extend:DI (match_operand:SI 1 "s_register_operand"))
 -            (sign_extend:DI (match_operand:SI 2 "s_register_operand")))
 +            (SE:DI (match_operand:SI 1 "s_register_operand"))
 +            (SE:DI (match_operand:SI 2 "s_register_operand")))
              (const_int 32))))
       (clobber (match_scratch:SI 3 ""))])]
    "TARGET_32BIT"
    ""
  )
  
 -(define_insn "*smulsi3_highpart_nov6"
 -  [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
 +(define_insn "*<US>mull_high"
 +  [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r")
          (truncate:SI
           (lshiftrt:DI
            (mult:DI
 -          (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
 -          (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
 +          (SE:DI (match_operand:SI 1 "s_register_operand" "%r,0,r"))
 +          (SE:DI (match_operand:SI 2 "s_register_operand" "r,r,r")))
            (const_int 32))))
 -   (clobber (match_scratch:SI 3 "=&r,&r"))]
 -  "TARGET_32BIT && !arm_arch6"
 -  "smull%?\\t%3, %0, %2, %1"
 -  [(set_attr "type" "smull")
 -   (set_attr "predicable" "yes")]
 -)
 -
 -(define_insn "*smulsi3_highpart_v6"
 -  [(set (match_operand:SI 0 "s_register_operand" "=r")
 -       (truncate:SI
 -        (lshiftrt:DI
 -         (mult:DI
 -          (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
 -          (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
 -         (const_int 32))))
 -   (clobber (match_scratch:SI 3 "=r"))]
 -  "TARGET_32BIT && arm_arch6"
 -  "smull%?\\t%3, %0, %2, %1"
 -  [(set_attr "type" "smull")
 -   (set_attr "predicable" "yes")]
 -)
 -
 -(define_expand "umulsi3_highpart"
 -  [(parallel
 -    [(set (match_operand:SI 0 "s_register_operand")
 -         (truncate:SI
 -          (lshiftrt:DI
 -           (mult:DI
 -            (zero_extend:DI (match_operand:SI 1 "s_register_operand"))
 -             (zero_extend:DI (match_operand:SI 2 "s_register_operand")))
 -           (const_int 32))))
 -     (clobber (match_scratch:SI 3 ""))])]
 +   (clobber (match_scratch:SI 3 "=r,&r,&r"))]
    "TARGET_32BIT"
 -  ""
 -)
 -
 -(define_insn "*umulsi3_highpart_nov6"
 -  [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
 -       (truncate:SI
 -        (lshiftrt:DI
 -         (mult:DI
 -          (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
 -          (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
 -         (const_int 32))))
 -   (clobber (match_scratch:SI 3 "=&r,&r"))]
 -  "TARGET_32BIT && !arm_arch6"
 -  "umull%?\\t%3, %0, %2, %1"
 +  "<US>mull%?\\t%3, %0, %2, %1"
    [(set_attr "type" "umull")
 -   (set_attr "predicable" "yes")]
 -)
 -
 -(define_insn "*umulsi3_highpart_v6"
 -  [(set (match_operand:SI 0 "s_register_operand" "=r")
 -       (truncate:SI
 -        (lshiftrt:DI
 -         (mult:DI
 -          (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
 -          (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
 -         (const_int 32))))
 -   (clobber (match_scratch:SI 3 "=r"))]
 -  "TARGET_32BIT && arm_arch6"
 -  "umull%?\\t%3, %0, %2, %1"
 -  [(set_attr "type" "umull")
 -   (set_attr "predicable" "yes")]
 +   (set_attr "predicable" "yes")
 +   (set_attr "arch" "v6,nov6,nov6")]
  )
  
  (define_insn "mulhisi3"

Kyrill Tkachov Sept. 18, 2019, 4:31 p.m. UTC | #2

Hi Wilco,

On 9/9/19 6:07 PM, Wilco Dijkstra wrote:
> ping
>
>
> Cleanup the various highpart multiply patterns using iterators.
>  As a result the signed and unsigned variants and the pre-Armv6
>  multiply operand constraints are all handled in a single pattern
>  and simple expander.
>
>  Bootstrap OK on armhf, regress passes.
>

Ok.

Thanks,

Kyrill


>  ChangeLog:
>  2019-09-03  Wilco Dijkstra  <wdijkstr@arm.com>
>
>          * config/arm/arm.md (smulsi3_highpart): Use <US> and <SE> 
> iterators.
>          (smulsi3_highpart_nov6): Remove pattern.
>          (smulsi3_highpart_v6): Likewise.
>          (umulsi3_highpart): Likewise.
>          (umulsi3_highpart_nov6): Likewise.
>          (umulsi3_highpart_v6): Likewise.
>          (<US>mull_high): Add new combined multiply pattern.
>  --
>  diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
>  index 
> 681358512e88f6823d1b6d59038f387daaec226e..1ab203810bf143927a8afa0d00d82537cd7c75ed 
> 100644
>  --- a/gcc/config/arm/arm.md
>  +++ b/gcc/config/arm/arm.md
>  @@ -1776,92 +1776,34 @@ (define_insn "*umulsidi3adddi_v6"
>      (set_attr "predicable" "yes")]
>   )
>
>  -(define_expand "smulsi3_highpart"
>  +(define_expand "<US>mulsi3_highpart"
>     [(parallel
>       [(set (match_operand:SI 0 "s_register_operand")
>             (truncate:SI
>              (lshiftrt:DI
>               (mult:DI
>  -            (sign_extend:DI (match_operand:SI 1 "s_register_operand"))
>  -            (sign_extend:DI (match_operand:SI 2 "s_register_operand")))
>  +            (SE:DI (match_operand:SI 1 "s_register_operand"))
>  +            (SE:DI (match_operand:SI 2 "s_register_operand")))
>               (const_int 32))))
>        (clobber (match_scratch:SI 3 ""))])]
>     "TARGET_32BIT"
>     ""
>   )
>
>  -(define_insn "*smulsi3_highpart_nov6"
>  -  [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
>  +(define_insn "*<US>mull_high"
>  +  [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r")
>           (truncate:SI
>            (lshiftrt:DI
>             (mult:DI
>  -          (sign_extend:DI (match_operand:SI 1 "s_register_operand" 
> "%0,r"))
>  -          (sign_extend:DI (match_operand:SI 2 "s_register_operand" 
> "r,r")))
>  +          (SE:DI (match_operand:SI 1 "s_register_operand" "%r,0,r"))
>  +          (SE:DI (match_operand:SI 2 "s_register_operand" "r,r,r")))
>             (const_int 32))))
>  -   (clobber (match_scratch:SI 3 "=&r,&r"))]
>  -  "TARGET_32BIT && !arm_arch6"
>  -  "smull%?\\t%3, %0, %2, %1"
>  -  [(set_attr "type" "smull")
>  -   (set_attr "predicable" "yes")]
>  -)
>  -
>  -(define_insn "*smulsi3_highpart_v6"
>  -  [(set (match_operand:SI 0 "s_register_operand" "=r")
>  -       (truncate:SI
>  -        (lshiftrt:DI
>  -         (mult:DI
>  -          (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
>  -          (sign_extend:DI (match_operand:SI 2 "s_register_operand" 
> "r")))
>  -         (const_int 32))))
>  -   (clobber (match_scratch:SI 3 "=r"))]
>  -  "TARGET_32BIT && arm_arch6"
>  -  "smull%?\\t%3, %0, %2, %1"
>  -  [(set_attr "type" "smull")
>  -   (set_attr "predicable" "yes")]
>  -)
>  -
>  -(define_expand "umulsi3_highpart"
>  -  [(parallel
>  -    [(set (match_operand:SI 0 "s_register_operand")
>  -         (truncate:SI
>  -          (lshiftrt:DI
>  -           (mult:DI
>  -            (zero_extend:DI (match_operand:SI 1 "s_register_operand"))
>  -             (zero_extend:DI (match_operand:SI 2 "s_register_operand")))
>  -           (const_int 32))))
>  -     (clobber (match_scratch:SI 3 ""))])]
>  +   (clobber (match_scratch:SI 3 "=r,&r,&r"))]
>     "TARGET_32BIT"
>  -  ""
>  -)
>  -
>  -(define_insn "*umulsi3_highpart_nov6"
>  -  [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
>  -       (truncate:SI
>  -        (lshiftrt:DI
>  -         (mult:DI
>  -          (zero_extend:DI (match_operand:SI 1 "s_register_operand" 
> "%0,r"))
>  -          (zero_extend:DI (match_operand:SI 2 "s_register_operand" 
> "r,r")))
>  -         (const_int 32))))
>  -   (clobber (match_scratch:SI 3 "=&r,&r"))]
>  -  "TARGET_32BIT && !arm_arch6"
>  -  "umull%?\\t%3, %0, %2, %1"
>  +  "<US>mull%?\\t%3, %0, %2, %1"
>     [(set_attr "type" "umull")
>  -   (set_attr "predicable" "yes")]
>  -)
>  -
>  -(define_insn "*umulsi3_highpart_v6"
>  -  [(set (match_operand:SI 0 "s_register_operand" "=r")
>  -       (truncate:SI
>  -        (lshiftrt:DI
>  -         (mult:DI
>  -          (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
>  -          (zero_extend:DI (match_operand:SI 2 "s_register_operand" 
> "r")))
>  -         (const_int 32))))
>  -   (clobber (match_scratch:SI 3 "=r"))]
>  -  "TARGET_32BIT && arm_arch6"
>  -  "umull%?\\t%3, %0, %2, %1"
>  -  [(set_attr "type" "umull")
>  -   (set_attr "predicable" "yes")]
>  +   (set_attr "predicable" "yes")
>  +   (set_attr "arch" "v6,nov6,nov6")]
>   )
>
>   (define_insn "mulhisi3"
>

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 681358512e88f6823d1b6d59038f387daaec226e..1ab203810bf143927a8afa0d00d82537cd7c75ed 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1776,92 +1776,34 @@  (define_insn "*umulsidi3adddi_v6"
    (set_attr "predicable" "yes")]
 )
 
-(define_expand "smulsi3_highpart"
+(define_expand "<US>mulsi3_highpart"
   [(parallel
     [(set (match_operand:SI 0 "s_register_operand")
 	  (truncate:SI
 	   (lshiftrt:DI
 	    (mult:DI
-	     (sign_extend:DI (match_operand:SI 1 "s_register_operand"))
-	     (sign_extend:DI (match_operand:SI 2 "s_register_operand")))
+	     (SE:DI (match_operand:SI 1 "s_register_operand"))
+	     (SE:DI (match_operand:SI 2 "s_register_operand")))
 	    (const_int 32))))
      (clobber (match_scratch:SI 3 ""))])]
   "TARGET_32BIT"
   ""
 )
 
-(define_insn "*smulsi3_highpart_nov6"
-  [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
+(define_insn "*<US>mull_high"
+  [(set (match_operand:SI 0 "s_register_operand" "=r,&r,&r")
 	(truncate:SI
 	 (lshiftrt:DI
 	  (mult:DI
-	   (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
-	   (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
+	   (SE:DI (match_operand:SI 1 "s_register_operand" "%r,0,r"))
+	   (SE:DI (match_operand:SI 2 "s_register_operand" "r,r,r")))
 	  (const_int 32))))
-   (clobber (match_scratch:SI 3 "=&r,&r"))]
-  "TARGET_32BIT && !arm_arch6"
-  "smull%?\\t%3, %0, %2, %1"
-  [(set_attr "type" "smull")
-   (set_attr "predicable" "yes")]
-)
-
-(define_insn "*smulsi3_highpart_v6"
-  [(set (match_operand:SI 0 "s_register_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI
-	  (mult:DI
-	   (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
-	   (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
-	  (const_int 32))))
-   (clobber (match_scratch:SI 3 "=r"))]
-  "TARGET_32BIT && arm_arch6"
-  "smull%?\\t%3, %0, %2, %1"
-  [(set_attr "type" "smull")
-   (set_attr "predicable" "yes")]
-)
-
-(define_expand "umulsi3_highpart"
-  [(parallel
-    [(set (match_operand:SI 0 "s_register_operand")
-	  (truncate:SI
-	   (lshiftrt:DI
-	    (mult:DI
-	     (zero_extend:DI (match_operand:SI 1 "s_register_operand"))
-	      (zero_extend:DI (match_operand:SI 2 "s_register_operand")))
-	    (const_int 32))))
-     (clobber (match_scratch:SI 3 ""))])]
+   (clobber (match_scratch:SI 3 "=r,&r,&r"))]
   "TARGET_32BIT"
-  ""
-)
-
-(define_insn "*umulsi3_highpart_nov6"
-  [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
-	(truncate:SI
-	 (lshiftrt:DI
-	  (mult:DI
-	   (zero_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r"))
-	   (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
-	  (const_int 32))))
-   (clobber (match_scratch:SI 3 "=&r,&r"))]
-  "TARGET_32BIT && !arm_arch6"
-  "umull%?\\t%3, %0, %2, %1"
+  "<US>mull%?\\t%3, %0, %2, %1"
   [(set_attr "type" "umull")
-   (set_attr "predicable" "yes")]
-)
-
-(define_insn "*umulsi3_highpart_v6"
-  [(set (match_operand:SI 0 "s_register_operand" "=r")
-	(truncate:SI
-	 (lshiftrt:DI
-	  (mult:DI
-	   (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
-	   (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
-	  (const_int 32))))
-   (clobber (match_scratch:SI 3 "=r"))]
-  "TARGET_32BIT && arm_arch6"
-  "umull%?\\t%3, %0, %2, %1"
-  [(set_attr "type" "umull")
-   (set_attr "predicable" "yes")]
+   (set_attr "predicable" "yes")
+   (set_attr "arch" "v6,nov6,nov6")]
 )
 
 (define_insn "mulhisi3"