From patchwork Tue Sep 3 03:32:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Reddy X-Patchwork-Id: 1156788 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="FPAITNo3"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46MstC05gBz9sNk for ; Tue, 3 Sep 2019 13:30:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726481AbfICDaf (ORCPT ); Mon, 2 Sep 2019 23:30:35 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:18235 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725955AbfICDae (ORCPT ); Mon, 2 Sep 2019 23:30:34 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 02 Sep 2019 20:30:36 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 02 Sep 2019 20:30:33 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 02 Sep 2019 20:30:33 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 3 Sep 2019 03:30:33 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 3 Sep 2019 03:30:33 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 02 Sep 2019 20:30:33 -0700 From: Krishna Reddy CC: , , , , , , , , , , , , , , , , , Krishna Reddy Subject: [PATCH v2 3/7] dt-bindings: arm-smmu: Add binding for Tegra194 SMMU Date: Mon, 2 Sep 2019 20:32:04 -0700 Message-ID: <1567481528-31163-4-git-send-email-vdumpa@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1567481528-31163-1-git-send-email-vdumpa@nvidia.com> References: <1567481528-31163-1-git-send-email-vdumpa@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1567481436; bh=BV/LVgUN0xHjgSMIibi1yi6G1q+IKS5HgMsw2hIF8KU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=FPAITNo3jTpQCsJ6yPvFI7nqNjUmJRyDoAQC4R80H1MiBfbERasqQINGII4+2PDZP F8lZUj8i1YoeOIhWEnTUwDYeBt6JlWKEt6mG8nRG/s+X7bxfjR4aMgN1a448qqpPv7 EMWJdwFrDPbPt6HA9mIBqSWXSRqpokI5jGeveTXhc2ZEcivHMEaLBKgusqlSxCI7/I 08CfebHYvN4UohyU0ADwwkn2FON8zejiT/Ol4YyDpzfK+RZ0BIMU1qGIM8JvO19HYe eDLZlB8o/QBTV82lyHpQq4xi10NoUjThySi/tdzaQjmsqXMKY7g0/fAKxbjRhPvKR7 PmXASHs/QS/9A== To: unlisted-recipients:; (no To-header on input) Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add binding for NVIDIA's Tegra194 Soc SMMU that is based on ARM MMU-500. Signed-off-by: Krishna Reddy --- Documentation/devicetree/bindings/iommu/arm,smmu.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 3133f3b..1d72fac 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -31,6 +31,10 @@ conditions. as below, SoC-specific compatibles: "qcom,sdm845-smmu-500", "arm,mmu-500" + NVIDIA SoCs that use more than one ARM MMU-500 together + needs following SoC-specific compatibles along with "arm,mmu-500": + "nvidia,tegra194-smmu" + - reg : Base address and size of the SMMU. - #global-interrupts : The number of global interrupts exposed by the