[OpenWrt-Devel,lantiq] general help on AR10 platform
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  • [OpenWrt-Devel,lantiq] general help on AR10 platform
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Enrico Mioso Sept. 2, 2019, 3:38 a.m. UTC
Hello guys,
Hello Hauke,

Sorry for the amount of mails.

So in I patched the kernel to be more specific on PMU error messages, since it seems something is fundamentally wrong here:
the system panics like

[    0.000000] SoC: xRX300 rev 1.2
[    0.000000] bootconsole [early0] enabled
[    0.000000] CPU0 revision is: 00019556 (MIPS 34Kc)
[    0.000000] MIPS: machine is AVM FRITZ!Box 3272
[    0.000000] Determined physical RAM map:
[    0.000000]  memory: 08000000 @ 00000000 (usable)
[    0.000000] Initrd not found or empty - disabling initrd
[    0.000000] Detected 1 available secondary CPU(s)
[    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000000000-0x0000000007ffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x0000000007ffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
[    0.000000] random: get_random_bytes called from start_kernel+0x98/0x4dc with crng_init=0
[    0.000000] percpu: Embedded 14 pages/cpu s26256 r8192 d22896 u57344
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32480
[    0.000000] Kernel command line: 
[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[    0.000000] Writing ErrCtl register=00050000
[    0.000000] Readback ErrCtl register=00050000
[    0.000000] Memory: 119048K/131072K available (5210K kernel code, 241K rwdata, 1524K rodata, 3376K init, 232K bss, 12024K reserved, 0K cma-reserved)
[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] NR_IRQS: 256
[    0.000000] deactivating PMU module 0 (clock gate) failed!
[    0.000000] deactivating PMU module 0 (clock gate) failed!
[    0.000000] deactivating PMU module 0 (clock gate) failed!
[    0.000000] deactivating PMU module 0 (clock gate) failed!
[    0.000000] deactivating PMU module 0 (clock gate) failed!
[    0.000000] deactivating PMU module 0 (clock gate) failed!
[    0.000000] CPU Clock: 333MHz
[    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 11467562725 ns
[    0.000018] sched_clock: 32 bits at 166MHz, resolution 6ns, wraps every 12884901885ns
[    0.012011] Calibrating delay loop... 221.18 BogoMIPS (lpj=442368)
[    0.061193] pid_max: default: 32768 minimum: 301
[    0.068648] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.078418] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.094717] rcu: Hierarchical SRCU implementation.
[    0.107625] smp: Bringing up secondary CPUs ...
[    0.116227] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.116249] Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes
[    0.116461] CPU1 revision is: 00019556 (MIPS 34Kc)
[    0.154663] Synchronize counters for CPU 1: done.
[    0.191216] smp: Brought up 1 node, 2 CPUs
[    0.202371] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.216869] futex hash table entries: 512 (order: 2, 16384 bytes)
[    0.226527] pinctrl core: initialized pinctrl subsystem
[    0.237723] NET: Registered protocol family 16
[    0.265485] dcdc-xrx200 1f106a00.dcdc: Core Voltage : 2040 mV
[    0.284748] pinctrl-xway 1e100b10.pinmux: Init done
[    0.393384] Kernel panic - not syncing: activating PMU module 0 (clock gate) failed!
[    0.404809] Rebooting in 1 seconds..
[    2.865738] Reboot failed -- System halted

Secondly, I am encountering some issues in
int __init lq_gptu_init(void)
... 
infact vendor firmware is not using
as I get a data abort at line 798 which reads:
timer_dev.number_of_timers = GPTU_ID_CFG * 2;

and looking at the vendor firmware, they do something like
timer_dev.number_of_timers = 3 * 2;

Where may I check for wrong things?
Thanks!!

Enrico

From 23bc8dd1d48bf7588f3aca1bf90c3999c0d05bcd Mon Sep 17 00:00:00 2001
From: Enrico Mioso <mrkiko.rs@gmail.com>
Date: Mon, 2 Sep 2019 05:04:19 +0200
Subject: [PATCH] lantiq: XWAY: report PMU module for which
  activation/deactivation failed

Helps in diagnosing issues when porting new devices.

Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
---
  arch/mips/lantiq/xway/sysctrl.c | 8 ++++----
  1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Enrico Mioso Sept. 2, 2019, 4:26 a.m. UTC | #1
BTW, in vendor's cgu_init, seems the "enablement" part is commented out.

static int __init cgu_init(void)
{
     int ret;
     char ver_str[128] = {0};

     ret = register_chrdev(IFX_CGU_MAJOR, "ifx_cgu", &cgu_fops);
     if ( ret != 0 ) {
         printk(KERN_ERR "Can not register CGU device - %d\n", ret);
         return ret;
     }

#ifdef CONFIG_PROC_FS
     proc_file_create();
#endif

     /* malloc MPS backup mem */
     argv = kmalloc(MPS_MEM_SEG_DATASIZE, GFP_KERNEL);

     ifx_cgu_version(ver_str);
     printk(KERN_INFO "%s", ver_str);

     //enable
     return IFX_SUCCESS;
}
Hauke Mehrtens Sept. 2, 2019, 6:29 p.m. UTC | #2
On 9/2/19 6:26 AM, Enrico Mioso wrote:
> BTW, in vendor's cgu_init, seems the "enablement" part is commented out.
> 
> static int __init cgu_init(void)
> {
>     int ret;
>     char ver_str[128] = {0};
> 
>     ret = register_chrdev(IFX_CGU_MAJOR, "ifx_cgu", &cgu_fops);
>     if ( ret != 0 ) {
>         printk(KERN_ERR "Can not register CGU device - %d\n", ret);
>         return ret;
>     }
> 
> #ifdef CONFIG_PROC_FS
>     proc_file_create();
> #endif
> 
>     /* malloc MPS backup mem */
>     argv = kmalloc(MPS_MEM_SEG_DATASIZE, GFP_KERNEL);
> 
>     ifx_cgu_version(ver_str);
>     printk(KERN_INFO "%s", ver_str);
> 
>     //enable
>     return IFX_SUCCESS;
> }
This is only registering some shar device to user space, nothing important.

Hauke
Hauke Mehrtens Sept. 2, 2019, 6:41 p.m. UTC | #3
On 9/2/19 5:38 AM, Enrico Mioso wrote:
> Hello guys,
> Hello Hauke,
> 
> Sorry for the amount of mails.

Did you had a look at this vendor device tree file:
https://gitlab.com/gplmirror/telekom-speedport-w925v/blob/master/w925_1.5.001.7_opensource/extern/lantiq-bsp/ugw711-grx550/UGW-7.1.1-SW-CD/Sources/UGW-7.1.1/ugw/target/linux/lantiq/dts/xRX330.dtsi

The arch code is added by these patches on top of kernel 3.10.X:
https://gitlab.com/gplmirror/telekom-speedport-w925v/tree/master/w925_1.5.001.7_opensource/extern/lantiq-bsp/ugw711-grx550/UGW-7.1.1-SW-CD/Sources/UGW-7.1.1/ugw/target/linux/lantiq/patches-3.10

The AR10 is probably partly working wih these kernel patches.

> So in I patched the kernel to be more specific on PMU error messages,
> since it seems something is fundamentally wrong here:
> the system panics like
> 
> [    0.000000] SoC: xRX300 rev 1.2
> [    0.000000] bootconsole [early0] enabled

Do you use the compatible string lantiq,ar10 for the device?

> [    0.000000] CPU0 revision is: 00019556 (MIPS 34Kc)
> [    0.000000] MIPS: machine is AVM FRITZ!Box 3272
> [    0.000000] Determined physical RAM map:
> [    0.000000]  memory: 08000000 @ 00000000 (usable)
> [    0.000000] Initrd not found or empty - disabling initrd
> [    0.000000] Detected 1 available secondary CPU(s)
> [    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32
> bytes.
> [    0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases,
> linesize 32 bytes
> [    0.000000] Zone ranges:
> [    0.000000]   Normal   [mem 0x0000000000000000-0x0000000007ffffff]
> [    0.000000] Movable zone start for each node
> [    0.000000] Early memory node ranges
> [    0.000000]   node   0: [mem 0x0000000000000000-0x0000000007ffffff]
> [    0.000000] Initmem setup node 0 [mem
> 0x0000000000000000-0x0000000007ffffff]
> [    0.000000] random: get_random_bytes called from
> start_kernel+0x98/0x4dc with crng_init=0
> [    0.000000] percpu: Embedded 14 pages/cpu s26256 r8192 d22896 u57344
> [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32480
> [    0.000000] Kernel command line: [    0.000000] Dentry cache hash
> table entries: 16384 (order: 4, 65536 bytes)
> [    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
> [    0.000000] Writing ErrCtl register=00050000
> [    0.000000] Readback ErrCtl register=00050000
> [    0.000000] Memory: 119048K/131072K available (5210K kernel code,
> 241K rwdata, 1524K rodata, 3376K init, 232K bss, 12024K reserved, 0K
> cma-reserved)
> [    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
> [    0.000000] rcu: Hierarchical RCU implementation.
> [    0.000000] NR_IRQS: 256
> [    0.000000] deactivating PMU module 0 (clock gate) failed!
> [    0.000000] deactivating PMU module 0 (clock gate) failed!
> [    0.000000] deactivating PMU module 0 (clock gate) failed!
> [    0.000000] deactivating PMU module 0 (clock gate) failed!
> [    0.000000] deactivating PMU module 0 (clock gate) failed!
> [    0.000000] deactivating PMU module 0 (clock gate) failed!

Did you add the PUM like this:

		pmu0: pmu@102000 {
			compatible = "lantiq,pmu-xway";
			reg = <0x102000 0x1000>;
		};

Please share your device tree and the other changes you did.

> [    0.000000] CPU Clock: 333MHz
> [    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 11467562725 ns
> [    0.000018] sched_clock: 32 bits at 166MHz, resolution 6ns, wraps
> every 12884901885ns
> [    0.012011] Calibrating delay loop... 221.18 BogoMIPS (lpj=442368)
> [    0.061193] pid_max: default: 32768 minimum: 301
> [    0.068648] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [    0.078418] Mountpoint-cache hash table entries: 1024 (order: 0, 4096
> bytes)
> [    0.094717] rcu: Hierarchical SRCU implementation.
> [    0.107625] smp: Bringing up secondary CPUs ...
> [    0.116227] Primary instruction cache 32kB, VIPT, 4-way, linesize 32
> bytes.
> [    0.116249] Primary data cache 32kB, 4-way, VIPT, cache aliases,
> linesize 32 bytes
> [    0.116461] CPU1 revision is: 00019556 (MIPS 34Kc)
> [    0.154663] Synchronize counters for CPU 1: done.
> [    0.191216] smp: Brought up 1 node, 2 CPUs
> [    0.202371] clocksource: jiffies: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 7645041785100000 ns
> [    0.216869] futex hash table entries: 512 (order: 2, 16384 bytes)
> [    0.226527] pinctrl core: initialized pinctrl subsystem
> [    0.237723] NET: Registered protocol family 16
> [    0.265485] dcdc-xrx200 1f106a00.dcdc: Core Voltage : 2040 mV
> [    0.284748] pinctrl-xway 1e100b10.pinmux: Init done
> [    0.393384] Kernel panic - not syncing: activating PMU module 0
> (clock gate) failed!
> [    0.404809] Rebooting in 1 seconds..
> [    2.865738] Reboot failed -- System halted
> 
> Secondly, I am encountering some issues in
> int __init lq_gptu_init(void)
> ... infact vendor firmware is not using
> as I get a data abort at line 798 which reads:
> timer_dev.number_of_timers = GPTU_ID_CFG * 2;
> 
> and looking at the vendor firmware, they do something like
> timer_dev.number_of_timers = 3 * 2;
> 
> Where may I check for wrong things?
> Thanks!!
> 
> Enrico
> 
> From 23bc8dd1d48bf7588f3aca1bf90c3999c0d05bcd Mon Sep 17 00:00:00 2001
> From: Enrico Mioso <mrkiko.rs@gmail.com>
> Date: Mon, 2 Sep 2019 05:04:19 +0200
> Subject: [PATCH] lantiq: XWAY: report PMU module for which
>  activation/deactivation failed
> 
> Helps in diagnosing issues when porting new devices.
> 
> Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
> ---
>  arch/mips/lantiq/xway/sysctrl.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/mips/lantiq/xway/sysctrl.c
> b/arch/mips/lantiq/xway/sysctrl.c
> index c7f6dee..b30fdcc 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -165,7 +165,7 @@ void ltq_pmu_enable(unsigned int module)
>      spin_unlock(&g_pmu_lock);
> 
>      if (!retry)
> -        panic("activating PMU module failed!");
> +        panic("activating PMU module %u failed!",module);
>  }
>  EXPORT_SYMBOL(ltq_pmu_enable);
> 
> @@ -180,7 +180,7 @@ void ltq_pmu_disable(unsigned int module)
>      spin_unlock(&g_pmu_lock);
> 
>      if (!retry)
> -        pr_warn("deactivating PMU module failed!");
> +        pr_warn("deactivating PMU module %u failed!",module);
>  }
>  EXPORT_SYMBOL(ltq_pmu_disable);
> 
> @@ -218,7 +218,7 @@ static int pmu_enable(struct clk *clk)
>      }
> 
>      if (!retry)
> -        panic("activating PMU module failed!");
> +        panic("activating PMU module %u (clock gate)
> failed!",clk->module);
> 
>      return 0;
>  }
> @@ -243,7 +243,7 @@ static void pmu_disable(struct clk *clk)
>      }
> 
>      if (!retry)
> -        pr_warn("deactivating PMU module failed!");
> +        pr_warn("deactivating PMU module %u (clock gate)
> failed!",clk->module);
>  }
> 
>  static void usb_set_clock(void)
Enrico Mioso Sept. 3, 2019, 4:44 a.m. UTC | #4
Dear Hauke,

Thanks!!

thank you for pointing me out at the teleko-speedport source code! I will compare and look at this very soon today.

So, with your help guys, I started from the vendor code in here:
http://osp.avm.de/fritzbox/fritzbox-3272/source-files-FRITZ.Box_3272-06.20.tar.gz

And started by writing an "arx300.dtsi" ifle - comparing with Bjorn's work, who he nicely provided, pointing me at it.
And pointing out I was using the wrong ebu address.

target/linux/lantiq/files/arch/mips/boot/dts/arx300.dtsi looks like:
#include <dt-bindings/gpio/gpio.h>

/ {
 	#address-cells = <1>;
 	#size-cells = <1>;
 	compatible = "lantiq,xway", "lantiq,ar10";

 	aliases {
 		serial0 = &asc1;
 	};

 	chosen {
 		stdout-path = "serial0:115200n8";
 	};

 	cpus {
 		cpu@0 {
 			compatible = "mips,mips34Kc";
 		};
 		cpu@1 {
 			compatible = "mips,mips34Kc";
 		};
 	};

 	memory@0 {
 		device_type = "memory";
 	};

 	cputemp@0 {
 		compatible = "lantiq,cputemp";
 	};

 	biu@1f800000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "lantiq,biu", "simple-bus";
 		reg = <0x1f800000 0x800000>;
 		ranges = <0x0 0x1f800000 0x7fffff>;

 		icu0: icu@80200 {
 			#interrupt-cells = <1>;
 			interrupt-controller;
 			compatible = "lantiq,icu";
 			reg = <0x80200 0x28
 				0x80228 0x28
 				0x80250 0x28
 				0x80278 0x28
 				0x802a0 0x28>;
 		};

 		watchdog@803f0 {
 			compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt";
 			reg = <0x803f0 0x10>;

 			regmap = <&rcu0>;
 		};
 	};

 	sram@1f000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "lantiq,sram", "simple-bus";
 		reg = <0x1f000000 0x800000>;
 		ranges = <0x0 0x1f000000 0x7fffff>;

 		eiu0: eiu@101000 {
 			#interrupt-cells = <1>;
 			interrupt-controller;
 			compatible = "lantiq,eiu-xway";
 			reg = <0x101000 0x1000>;
 			interrupt-parent = <&icu0>;
 			lantiq,eiu-irqs = <166 135 66 40 41 42>;
 		};

 		pmu0: pmu@102000 {
 			compatible = "lantiq,pmu-xway";
 			reg = <0x102000 0x1000>;
 		};

 		cgu0: cgu@103000 {
 			compatible = "lantiq,cgu-xway";
 			reg = <0x103000 0x1000>;
 		};

 		dcdc@106a00 {
 			compatible = "lantiq,dcdc-xrx200";
 			reg = <0x106a00 0x200>;
 		};

 		rcu0: rcu@203000 {
 			compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
 			reg = <0x203000 0x100>;
 			ranges = <0x0 0x203000 0x100>;
 			big-endian;

 			gphy0: gphy@20 {
 				compatible = "lantiq,xrx300-gphy";
 				reg = <0x20 0x4>;

 				resets = <&reset0 31 30>, <&reset1 7 7>;
 				reset-names = "gphy", "gphy2";
 			};

 			gphy1: gphy@58 {
 				compatible = "lantiq,xrx300-gphy";
 				reg = <0x58 0x4>;

 				resets = <&reset0 29 28>, <&reset1 6 6>;
 				reset-names = "gphy", "gphy2";
 			};

 			gphy2: gphy@ac {
 				compatible = "lantiq,xrx300-gphy";
 				reg = <0xac 0x4>;

 				resets = <&reset0 27 26>, <&reset1 5 5>;
 				reset-names = "gphy", "gphy2";
 			};

 			reset0: reset-controller@10 {
 				compatible = "lantiq,xrx200-reset";
 				reg = <0x10 4>, <0x14 4>;

 				#reset-cells = <2>;
 			};

 			reset1: reset-controller@48 {
 				compatible = "lantiq,xrx200-reset";
 				reg = <0x48 4>, <0x24 4>;

 				#reset-cells = <2>;
 			};

 			usb_phy0: usb2-phy@18 {
 				compatible = "lantiq,xrx300-usb2-phy";
 				reg = <0x18 4>, <0x38 4>;
 				status = "disabled";

 				resets = <&reset1 4 4>, <&reset0 4 4>;
 				reset-names = "phy", "ctrl";
 				#phy-cells = <0>;
 			};

 			usb_phy1: usb2-phy@34 {
 				compatible = "lantiq,xrx300-usb2-phy";
 				reg = <0x34 4>, <0x3c 4>;
 				status = "disabled";

 				resets = <&reset1 5 4>, <&reset0 4 4>;
 				reset-names = "phy", "ctrl";
 				#phy-cells = <0>;
 			};

 			reboot@10 {
 				compatible = "syscon-reboot";
 				reg = <0x10 4>;

 				regmap = <&rcu0>;
 				offset = <0x10>;
 				mask = <0xe0000000>;
 			};
 		};
 	};

 	fpi@10000000 {
 		compatible = "lantiq,xrx200-fpi", "simple-bus";
 		ranges = <0x0 0x10000000 0xf000000>;
 		reg =	<0x1f400000 0x1000>,
 			<0x10000000 0xf000000>;
 		regmap = <&rcu0>;
 		offset-endianness = <0x4c>;
 		#address-cells = <1>;
 		#size-cells = <1>;

 		localbus: localbus@0 {
 			#address-cells = <2>;
 			#size-cells = <1>;
 			ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
 				1 0 0x4000000 0x4000010>; /* addsel1 */
 			compatible = "lantiq,localbus", "simple-bus";
 		};

 		gptu@e100a00 {
 			compatible = "lantiq,gptu-xway";
 			reg = <0xe100a00 0x100>;
 			interrupt-parent = <&icu0>;
 			interrupts = <120 121 122 123 124 125>;
 		};

 		gpio: pinmux@e100b10 {
 			compatible = "lantiq,xrx300-pinctrl";
 			#gpio-cells = <2>;
 			gpio-controller;
 			reg = <0xe100b10 0xa0>;
 		};

 		stp: stp@e100bb0 {
 			status = "disabled";
 			compatible = "lantiq,gpio-stp-xway";
 			reg = <0xe100bb0 0x40>;
 			#gpio-cells = <2>;
 			gpio-controller;

 			lantiq,shadow = <0xffffff>;
 			lantiq,groups = <0x7>;
 			lantiq,dsl = <0x0>;
 			lantiq,phy1 = <0x0>;
 			lantiq,phy2 = <0x0>;
 		};

 		asc1: serial@e100c00 {
 			compatible = "lantiq,asc";
 			reg = <0xe100c00 0x400>;
 			interrupt-parent = <&icu0>;
 			interrupts = <105 107 108>;
 		};

 		deu@e103100 {
 			status = "disabled";
 			compatible = "lantiq,deu-xrx200";
 			reg = <0xe103100 0xf00>;
 		};

 		dma0: dma@e104100 {
 			compatible = "lantiq,dma-xway";
 			reg = <0xe104100 0x800>;
 		};

 		ebu0: ebu@6000000 {
 			compatible = "lantiq,ebu-xway";
 			reg = <0x6000000 0x100>;
 		};

 		eth0: eth@e108000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "lantiq,xrx200-net";
 			reg = <	0xe108000 0x3000 /* switch */
 				0xe10b100 0x70 /* mdio */
 				0xe10b1d8 0x30 /* mii */
 				0xe10b308 0x30 /* pmac */
 			>;
 			interrupt-parent = <&icu0>;
 			interrupts = <75 73 72>;
 			resets = <&reset0 21 16>, <&reset0 8 8>;
 			reset-names = "switch", "ppe";
 			lantiq,phys = <&gphy0>, <&gphy1>, <&gphy2>;
 		};

 		ppe@e234000 {
 			compatible = "lantiq,ppe-xrx200";
 			interrupt-parent = <&icu0>;
 			interrupts = <96>;
 		};
 	};

};


target/linux/lantiq/files/arch/mips/boot/dts/FRITZ3272.dts (a placeholder for now):

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;

#include "arx300.dtsi"

#include <dt-bindings/input/input.h>
#include <dt-bindings/mips/lantiq_rcu_gphy.h>

/ {
 	compatible = "avm,fritz3272", "lantiq,xway", "lantiq,arx300";
 	model = "AVM FRITZ!Box 3272";

 	memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x8000000>;
 	};
};



Thank you very very much for all the help!
Enrico


On Mon, 2 Sep 2019, Hauke Mehrtens wrote:

> Date: Mon, 2 Sep 2019 20:41:29
> From: Hauke Mehrtens <hauke@hauke-m.de>
> To: Enrico Mioso <mrkiko.rs@gmail.com>, openwrt-devel@lists.openwrt.org
> Subject: Re: [OpenWrt-Devel] [lantiq] general help on AR10 platform
> 
> On 9/2/19 5:38 AM, Enrico Mioso wrote:
>> Hello guys,
>> Hello Hauke,
>>
>> Sorry for the amount of mails.
>
> Did you had a look at this vendor device tree file:
> https://gitlab.com/gplmirror/telekom-speedport-w925v/blob/master/w925_1.5.001.7_opensource/extern/lantiq-bsp/ugw711-grx550/UGW-7.1.1-SW-CD/Sources/UGW-7.1.1/ugw/target/linux/lantiq/dts/xRX330.dtsi
>
> The arch code is added by these patches on top of kernel 3.10.X:
> https://gitlab.com/gplmirror/telekom-speedport-w925v/tree/master/w925_1.5.001.7_opensource/extern/lantiq-bsp/ugw711-grx550/UGW-7.1.1-SW-CD/Sources/UGW-7.1.1/ugw/target/linux/lantiq/patches-3.10
>
> The AR10 is probably partly working wih these kernel patches.
>
>> So in I patched the kernel to be more specific on PMU error messages,
>> since it seems something is fundamentally wrong here:
>> the system panics like
>>
>> [    0.000000] SoC: xRX300 rev 1.2
>> [    0.000000] bootconsole [early0] enabled
>
> Do you use the compatible string lantiq,ar10 for the device?
>
>> [    0.000000] CPU0 revision is: 00019556 (MIPS 34Kc)
>> [    0.000000] MIPS: machine is AVM FRITZ!Box 3272
>> [    0.000000] Determined physical RAM map:
>> [    0.000000]  memory: 08000000 @ 00000000 (usable)
>> [    0.000000] Initrd not found or empty - disabling initrd
>> [    0.000000] Detected 1 available secondary CPU(s)
>> [    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32
>> bytes.
>> [    0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases,
>> linesize 32 bytes
>> [    0.000000] Zone ranges:
>> [    0.000000]   Normal   [mem 0x0000000000000000-0x0000000007ffffff]
>> [    0.000000] Movable zone start for each node
>> [    0.000000] Early memory node ranges
>> [    0.000000]   node   0: [mem 0x0000000000000000-0x0000000007ffffff]
>> [    0.000000] Initmem setup node 0 [mem
>> 0x0000000000000000-0x0000000007ffffff]
>> [    0.000000] random: get_random_bytes called from
>> start_kernel+0x98/0x4dc with crng_init=0
>> [    0.000000] percpu: Embedded 14 pages/cpu s26256 r8192 d22896 u57344
>> [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32480
>> [    0.000000] Kernel command line: [    0.000000] Dentry cache hash
>> table entries: 16384 (order: 4, 65536 bytes)
>> [    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
>> [    0.000000] Writing ErrCtl register=00050000
>> [    0.000000] Readback ErrCtl register=00050000
>> [    0.000000] Memory: 119048K/131072K available (5210K kernel code,
>> 241K rwdata, 1524K rodata, 3376K init, 232K bss, 12024K reserved, 0K
>> cma-reserved)
>> [    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
>> [    0.000000] rcu: Hierarchical RCU implementation.
>> [    0.000000] NR_IRQS: 256
>> [    0.000000] deactivating PMU module 0 (clock gate) failed!
>> [    0.000000] deactivating PMU module 0 (clock gate) failed!
>> [    0.000000] deactivating PMU module 0 (clock gate) failed!
>> [    0.000000] deactivating PMU module 0 (clock gate) failed!
>> [    0.000000] deactivating PMU module 0 (clock gate) failed!
>> [    0.000000] deactivating PMU module 0 (clock gate) failed!
>
> Did you add the PUM like this:
>
> 		pmu0: pmu@102000 {
> 			compatible = "lantiq,pmu-xway";
> 			reg = <0x102000 0x1000>;
> 		};
>
> Please share your device tree and the other changes you did.
>
>> [    0.000000] CPU Clock: 333MHz
>> [    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles:
>> 0xffffffff, max_idle_ns: 11467562725 ns
>> [    0.000018] sched_clock: 32 bits at 166MHz, resolution 6ns, wraps
>> every 12884901885ns
>> [    0.012011] Calibrating delay loop... 221.18 BogoMIPS (lpj=442368)
>> [    0.061193] pid_max: default: 32768 minimum: 301
>> [    0.068648] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
>> [    0.078418] Mountpoint-cache hash table entries: 1024 (order: 0, 4096
>> bytes)
>> [    0.094717] rcu: Hierarchical SRCU implementation.
>> [    0.107625] smp: Bringing up secondary CPUs ...
>> [    0.116227] Primary instruction cache 32kB, VIPT, 4-way, linesize 32
>> bytes.
>> [    0.116249] Primary data cache 32kB, 4-way, VIPT, cache aliases,
>> linesize 32 bytes
>> [    0.116461] CPU1 revision is: 00019556 (MIPS 34Kc)
>> [    0.154663] Synchronize counters for CPU 1: done.
>> [    0.191216] smp: Brought up 1 node, 2 CPUs
>> [    0.202371] clocksource: jiffies: mask: 0xffffffff max_cycles:
>> 0xffffffff, max_idle_ns: 7645041785100000 ns
>> [    0.216869] futex hash table entries: 512 (order: 2, 16384 bytes)
>> [    0.226527] pinctrl core: initialized pinctrl subsystem
>> [    0.237723] NET: Registered protocol family 16
>> [    0.265485] dcdc-xrx200 1f106a00.dcdc: Core Voltage : 2040 mV
>> [    0.284748] pinctrl-xway 1e100b10.pinmux: Init done
>> [    0.393384] Kernel panic - not syncing: activating PMU module 0
>> (clock gate) failed!
>> [    0.404809] Rebooting in 1 seconds..
>> [    2.865738] Reboot failed -- System halted
>>
>> Secondly, I am encountering some issues in
>> int __init lq_gptu_init(void)
>> ... infact vendor firmware is not using
>> as I get a data abort at line 798 which reads:
>> timer_dev.number_of_timers = GPTU_ID_CFG * 2;
>>
>> and looking at the vendor firmware, they do something like
>> timer_dev.number_of_timers = 3 * 2;
>>
>> Where may I check for wrong things?
>> Thanks!!
>>
>> Enrico
>>
>> From 23bc8dd1d48bf7588f3aca1bf90c3999c0d05bcd Mon Sep 17 00:00:00 2001
>> From: Enrico Mioso <mrkiko.rs@gmail.com>
>> Date: Mon, 2 Sep 2019 05:04:19 +0200
>> Subject: [PATCH] lantiq: XWAY: report PMU module for which
>>  activation/deactivation failed
>>
>> Helps in diagnosing issues when porting new devices.
>>
>> Signed-off-by: Enrico Mioso <mrkiko.rs@gmail.com>
>> ---
>>  arch/mips/lantiq/xway/sysctrl.c | 8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/mips/lantiq/xway/sysctrl.c
>> b/arch/mips/lantiq/xway/sysctrl.c
>> index c7f6dee..b30fdcc 100644
>> --- a/arch/mips/lantiq/xway/sysctrl.c
>> +++ b/arch/mips/lantiq/xway/sysctrl.c
>> @@ -165,7 +165,7 @@ void ltq_pmu_enable(unsigned int module)
>>      spin_unlock(&g_pmu_lock);
>>
>>      if (!retry)
>> -        panic("activating PMU module failed!");
>> +        panic("activating PMU module %u failed!",module);
>>  }
>>  EXPORT_SYMBOL(ltq_pmu_enable);
>>
>> @@ -180,7 +180,7 @@ void ltq_pmu_disable(unsigned int module)
>>      spin_unlock(&g_pmu_lock);
>>
>>      if (!retry)
>> -        pr_warn("deactivating PMU module failed!");
>> +        pr_warn("deactivating PMU module %u failed!",module);
>>  }
>>  EXPORT_SYMBOL(ltq_pmu_disable);
>>
>> @@ -218,7 +218,7 @@ static int pmu_enable(struct clk *clk)
>>      }
>>
>>      if (!retry)
>> -        panic("activating PMU module failed!");
>> +        panic("activating PMU module %u (clock gate)
>> failed!",clk->module);
>>
>>      return 0;
>>  }
>> @@ -243,7 +243,7 @@ static void pmu_disable(struct clk *clk)
>>      }
>>
>>      if (!retry)
>> -        pr_warn("deactivating PMU module failed!");
>> +        pr_warn("deactivating PMU module %u (clock gate)
>> failed!",clk->module);
>>  }
>>
>>  static void usb_set_clock(void)
>
>
>
Enrico Mioso Sept. 3, 2019, 8:21 a.m. UTC | #5
Hey there!
On Mon, 2 Sep 2019, Hauke Mehrtens wrote:

> Do you use the compatible string lantiq,ar10 for the device?

OOOOPS! Thanks!!!! Lots of work needed but still...

Eva_AVM >   







........................................................................................[    0.000000] Linux version 4.19.68 (mrkiko@mStation) (gcc version 7.4.0 (OpenWrt GCC 7.4.0 r10891-055abe902b)) #0 SMP Thu Aug 29 14:19:00 2019
[    0.000000] SoC: xRX300 rev 1.2
[    0.000000] bootconsole [early0] enabled
[    0.000000] CPU0 revision is: 00019556 (MIPS 34Kc)
[    0.000000] MIPS: machine is AVM FRITZ!Box 3272
[    0.000000] Determined physical RAM map:
[    0.000000]  memory: 08000000 @ 00000000 (usable)
[    0.000000] Initrd not found or empty - disabling initrd
[    0.000000] Detected 1 available secondary CPU(s)
[    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000000000-0x0000000007ffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x0000000007ffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
[    0.000000] random: get_random_bytes called from start_kernel+0x98/0x4dc with crng_init=0
[    0.000000] percpu: Embedded 14 pages/cpu s26256 r8192 d22896 u57344
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32480
[    0.000000] Kernel command line: 
[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[    0.000000] Writing ErrCtl register=00050000
[    0.000000] Readback ErrCtl register=00050000
[    0.000000] Memory: 119044K/131072K available (5210K kernel code, 241K rwdata, 1524K rodata, 3376K init, 232K bss, 12028K reserved, 0K cma-reserved)
[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] NR_IRQS: 256
[    0.000000] CPU Clock: 500MHz
[    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041786 ns
[    0.000012] sched_clock: 32 bits at 250MHz, resolution 4ns, wraps every 8589934590ns
[    0.007922] Calibrating delay loop... 332.54 BogoMIPS (lpj=665088)
[    0.046022] pid_max: default: 32768 minimum: 301
[    0.050995] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.057507] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.068267] rcu: Hierarchical SRCU implementation.
[    0.076792] smp: Bringing up secondary CPUs ...
[    0.082535] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.082551] Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes
[    0.082694] CPU1 revision is: 00019556 (MIPS 34Kc)
[    0.113485] Synchronize counters for CPU 1: done.
[    0.137848] smp: Brought up 1 node, 2 CPUs
[    0.145295] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.154989] futex hash table entries: 512 (order: 2, 16384 bytes)
[    0.161374] pinctrl core: initialized pinctrl subsystem
[    0.168913] NET: Registered protocol family 16
[    0.192153] pinctrl-xway 1e100b10.pinmux: Init done
[    0.198381] dma-xway 1e104100.dma: Init done - hw rev: 8, ports: 5, channels: 24
[    0.242745] usbcore: registered new interface driver usbfs
[    0.248408] usbcore: registered new interface driver hub
[    0.253842] usbcore: registered new device driver usb
[    0.262539] clocksource: Switched to clocksource MIPS
[    0.270805] NET: Registered protocol family 2
[    0.276328] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
[    0.283934] TCP established hash table entries: 1024 (order: 0, 4096 bytes)
[    0.290964] TCP bind hash table entries: 1024 (order: 1, 8192 bytes)
[    0.297372] TCP: Hash tables configured (established 1024 bind 1024)
[    0.304011] UDP hash table entries: 256 (order: 1, 8192 bytes)
[    0.309805] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[    0.316470] NET: Registered protocol family 1
[    0.497491] random: fast init done
[    4.762312] gptu: totally 6 16-bit timers/counters
[    4.767177] gptu: misc_register on minor 63
[    4.771338] gptu: succeeded to request irq 126
[    4.775862] gptu: succeeded to request irq 127
[    4.780340] gptu: succeeded to request irq 128
[    4.784898] gptu: succeeded to request irq 129
[    4.789369] gptu: succeeded to request irq 130
[    4.793888] gptu: succeeded to request irq 131
[    4.798552] No VPEs reserved for AP/SP, not initialize VPE loader
[    4.798552] Pass maxvpes=<n> argument as kernel argument
[    4.809939] No TCs reserved for AP/SP, not initializing RTLX.
[    4.809939] Pass maxtcs=<n> argument as kernel argument
[    4.823144] Crashlog allocated RAM at address 0x3f00000
[    4.828818] workingset: timestamp_bits=14 max_order=15 bucket_order=1
[    4.853525] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    4.859312] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc.
[    4.882110] io scheduler noop registered
[    4.886082] io scheduler deadline registered (default)
[    4.892539] fpi-xway 10000000.fpi: can't request region for resource [mem 0x10000000-0x1fefffff]
[    4.901331] fpi-xway: probe of 10000000.fpi failed with error -16
[    4.908974] 1e100c00.serial: ttyLTQ0 at MMIO 0x1e100c00 (irq = 112, base_baud = 0) is a lantiq,asc
[    4.917888] console [ttyLTQ0] enabled
[    4.917888] console [ttyLTQ0] enabled
[    4.925235] bootconsole [early0] disabled
[    4.925235] bootconsole [early0] disabled
[    4.934787] cacheinfo: Failed to find cpu0 device node
[    4.938696] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    4.950104] libphy: Fixed MDIO Bus: probed
[    4.956849] wdt 1f8803f0.watchdog: Init done
[    4.963583] NET: Registered protocol family 10
[    4.971956] Segment Routing with IPv6
[    4.974549] NET: Registered protocol family 17
[    4.978846] 8021q: 802.1Q VLAN Support v1.8
[    4.998378] Freeing unused kernel memory: 3376K
[    5.001519] This architecture does not have kernel memory protection.
[    5.007949] Run /init as init process
[    5.032752] init: Console is alive
[    5.035243] init: - watchdog -
[    5.064201] kmodloader: loading kernel modules from /etc/modules-boot.d/*
[    5.073603] kmodloader: done loading kernel modules from /etc/modules-boot.d/*
[    5.089945] init: - preinit -
Press the [f] key and hit [enter] to enter failsafe mode
Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level
[    8.403771] procd: - early -
[    8.405405] procd: - watchdog -
[    8.984982] procd: - watchdog -
[    8.987423] procd: - ubus -
[    8.998940] random: ubusd: uninitialized urandom read (4 bytes read)
[    9.040099] random: ubusd: uninitialized urandom read (4 bytes read)
[    9.045911] random: ubusd: uninitialized urandom read (4 bytes read)
[    9.053860] procd: - init -
Please press Enter to activate this console.
[    9.602838] kmodloader: loading kernel modules from /etc/modules.d/*
[    9.612884] IFXOS, Version 1.5.19 (c) Copyright 2009, Lantiq Deutschland GmbH
[    9.625395] NET: Registered protocol family 8
[    9.628395] NET: Registered protocol family 20
[    9.644457] PPP generic driver version 2.4.2
[    9.698097] Lantiq (VRX) DSL CPE MEI driver, version 1.5.17.6, (c) 2007-2015 Lantiq Beteiligungs-GmbH & Co. KG
[    9.717819] 
[    9.717819] 
[    9.717819] Lantiq CPE API Driver version: DSL CPE API V4.17.18.6
[    9.735493] 
[    9.735493] Predefined debug level: 3
[    9.740625] Get BSP Driver Handle Fail!
[    9.744454] Get BSP Driver NFC Handle Fail!
[    9.756135] urngd: v1.0.0 started.
[    9.787304] NET: Registered protocol family 24
[    9.809358] xt_time: kernel timezone is -0000
[    9.871018] kmodloader: done loading kernel modules from /etc/modules.d/*
[   10.054261] random: crng init done
[   10.056226] random: 7 urandom warning(s) missed due to ratelimiting
Enrico Mioso Sept. 4, 2019, 10:07 a.m. UTC | #6
Hi there!

So I am trying to get ethernet working on this AR10 device.
It has 3 GPHYs:

 			gphy0: gphy@20 {
 				compatible = "lantiq,xrx300-gphy";
 				reg = <0x20 0x4>;

 				resets = <&reset0 31 30>, <&reset1 7 7>;
 				reset-names = "gphy", "gphy2";
 			};

 			gphy1: gphy@58 {
 				compatible = "lantiq,xrx300-gphy";
 				reg = <0x58 0x4>;

 				resets = <&reset0 29 28>, <&reset1 6 6>;
 				reset-names = "gphy", "gphy2";
 			};

 			gphy2: gphy@ac {
 				compatible = "lantiq,xrx300-gphy";
 				reg = <0xac 0x4>;
 				resets = <&reset0 27 26>, <&reset1 5 5>;
 				reset-names = "gphy", "gphy2";
 			};

And firmware load addresses for GPHYs are correct as per the vendor code:
#define IFX_RCU_GPHY0_FW_ADDR                   ((volatile u32*)(IFX_RCU + 0x0020))
#define IFX_RCU_GPHY1_FW_ADDR                   ((volatile u32*)(IFX_RCU + 0x0058))
#define IFX_RCU_GPHY2_FW_ADDR                   ((volatile u32*)(IFX_RCU + 0x00AC))

But driver was failing to initialize due to missing clock gates.
In sysctrl.c, we have:
clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY); // OK for GPHY0
clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY); //problem for GPHY1

And GPHY2?

Attaching complete AR10 DTS I obtained collecting informations from various sources.
I would ask you if you could kindly help me pointing out mistakes,.
I am sure I am accumulating a fair amount of useless stuff in this file.
Enrico

#include <dt-bindings/gpio/gpio.h>

/ {
 	#address-cells = <1>;
 	#size-cells = <1>;
 	compatible = "lantiq,xway", "lantiq,ar10";

 	aliases {
 		serial0 = &asc1;
 	};

 	chosen {
 		stdout-path = "serial0:115200n8";
 	};

 	cpus {
 		cpu@0 {
 			compatible = "mips,mips34Kc";
 		};
 		cpu@1 {
 			compatible = "mips,mips34Kc";
 		};
 	};

 	memory@0 {
 		device_type = "memory";
 	};

 	cputemp@0 {
 		compatible = "lantiq,cputemp";
 	};

 	biu@1f800000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "lantiq,biu", "simple-bus";
 		reg = <0x1f800000 0x800000>;
 		ranges = <0x0 0x1f800000 0x7fffff>;

 		icu0: icu0@80200 {
 			#interrupt-cells = <1>;
 			interrupt-controller;
 			compatible = "lantiq,icu";
 			reg = <0x80200 0x28
 				0x80228 0x28
 				0x80250 0x28
 				0x80278 0x28
 				0x802a0 0x28>;
 		};

 		icu1: icu1@80300 {
 			#interrupt-cells = <1>;
 			interrupt-controller;
 			compatible = "lantiq,icu1";
 			reg = <0x80300 0x28
 				0x80328 0x28
 				0x80350 0x28
 				0x80378 0x28
 				0x803a0 0x28>;
 		};

 		watchdog@803f0 {
 			compatible = "lantiq,xrx100-wdt";
 			reg = <0x803f0 0x10>;
 			regmap = <&rcu0>;
 		};
 	};

 	sram@1f000000 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "lantiq,sram", "simple-bus";
 		reg = <0x1f000000 0x800000>;
 		ranges = <0x0 0x1f000000 0x7fffff>;

 		eiu0: eiu@101000 {
 			#interrupt-cells = <1>;
 			interrupt-controller;
 			compatible = "lantiq,eiu-xway";
 			reg = <0x101000 0x1000>;
 			interrupt-parent = <&icu0>;
 			lantiq,eiu-irqs = <166 135 66 40 41 42>;
 		};

 		pmu0: pmu@102000 {
 			compatible = "lantiq,pmu-xway";
 			reg = <0x102000 0x1000>;
 		};

 		cgu0: cgu@103000 {
 			compatible = "lantiq,cgu-xway";
 			reg = <0x103000 0x1000>;
 		};

 		ts: ts@106f00 {
 			compatible = "lantiq,ts-grx390"; /* to revisit */
 			reg = <0x106f00 0x10>;
 			interrupt-parent = <&icu0>;
 			interrupts = <143>;
 			lantiq,numofsensors = <0x1>;
 		};

 		dcdc@106a00 {
 			compatible = "lantiq,dcdc-xrx200";
 			reg = <0x106a00 0x200>;
 		};

 		vmmc: vmmc@103000 {
 			status = "disabled";
 			compatible = "lantiq,vmmc-xway";
 			reg = <0x103000 0x400>;
 			interrupt-parent = <&icu0>;
 			interrupts = <150 151 152 153 154 155>;
 		};

 		rcu0: rcu@203000 {
 			compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
 			reg = <0x203000 0x1000>;
//			interrupt-parent = <&icu0>;
//			interrupts = <115>;
 			ranges = <0x0 0x203000 0x100>;
 			big-endian;

 			gphy0: gphy@20 {
 				compatible = "lantiq,xrx300-gphy";
 				reg = <0x20 0x4>;

 				resets = <&reset0 31 30>, <&reset1 7 7>;
 				reset-names = "gphy", "gphy2";
 			};

 			gphy1: gphy@58 {
 				compatible = "lantiq,xrx300-gphy";
 				reg = <0x58 0x4>;

 				resets = <&reset0 29 28>, <&reset1 6 6>;
 				reset-names = "gphy", "gphy2";
 			};

 			gphy2: gphy@ac {
 				compatible = "lantiq,xrx300-gphy";
 				reg = <0xac 0x4>;
 				resets = <&reset0 27 26>, <&reset1 5 5>;
 				reset-names = "gphy", "gphy2";
 			};

 			reset0: reset-controller@10 {
 				compatible = "lantiq,xrx200-reset";
 				reg = <0x10 4>, <0x14 4>;

 				#reset-cells = <2>;
 			};

 			reset1: reset-controller@48 {
 				compatible = "lantiq,xrx200-reset";
 				reg = <0x48 4>, <0x24 4>;

 				#reset-cells = <2>;
 			};

 			usb_phy0: usb2-phy@18 {
 				compatible = "lantiq,xrx300-usb2-phy";
 				reg = <0x18 4>, <0x38 4>;
 				status = "disabled";

 				resets = <&reset1 4 4>, <&reset0 4 4>;
 				reset-names = "phy", "ctrl";
 				#phy-cells = <0>;
 			};

 			usb_phy1: usb2-phy@34 {
 				compatible = "lantiq,xrx300-usb2-phy";
 				reg = <0x34 4>, <0x3c 4>;
 				status = "disabled";

 				resets = <&reset1 5 4>, <&reset0 4 4>;
 				reset-names = "phy", "ctrl";
 				#phy-cells = <0>;
 			};

 			reboot@10 {
 				compatible = "syscon-reboot";
 				reg = <0x10 4>;

 				regmap = <&rcu0>;
 				offset = <0x10>;
 				mask = <0xe0000000>;
 			};
 		};
 	};

 	fpi@10000000 {
 		compatible = "lantiq,xrx200-fpi", "simple-bus";
 		ranges = <0x0 0x10000000 0xff00000>;
 		reg = <0x1f400000 0x1000>,
 			<0x10000000 0xf000000>;
 		regmap = <&rcu0>;
 		offset-endianness = <0x4c>; /* ?????????? */
 		#address-cells = <1>;
 		#size-cells = <1>;

 		localbus: localbus@0 {
 			#address-cells = <2>;
 			#size-cells = <1>;
 			ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
 				1 0 0x4000000 0x4000010>; /* addsel1 */
 			compatible = "lantiq,localbus", "simple-bus";
 		};

 		gptu@e100a00 {
 			compatible = "lantiq,gptu-xway";
 			reg = <0xe100a00 0x100>;
 			interrupt-parent = <&icu0>;
 			interrupts = <126 127 128 129 130 131>;
 		};

 		usif: usif@da00000 {
 			compatible = "lantiq,usif";
 			reg = <0xda00000 0x1000000>;
 			interrupt-parent = <&icu0>;
 			interrupts = <29 125 107 108 109 110>;
 			status = "disabled";
 		};

 		spi: spi@e100800 {
 			compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
 			reg = <0xe100800 0x100>;
 			interrupt-parent = <&icu0>;
 			interrupts = <22 23 24>;
 			interrupt-names = "spi_rx", "spi_tx", "spi_err",
 				"spi_frm";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			status = "disabled";
 		};

 		asc1: serial@e100c00 {
 			compatible = "lantiq,asc";
 			reg = <0xe100c00 0x400>;
 			interrupt-parent = <&icu0>;
 			interrupts = <112 113 114>;
 		};

 		gpio: pinmux@e100b10 {
 			compatible = "lantiq,xrx300-pinctrl";
 			#gpio-cells = <2>;
 			gpio-controller;
 			reg = <0xe100b10 0xa0>;
 		};

 		stp: stp@e100bb0 {
 			status = "disabled";
 			compatible = "lantiq,gpio-stp-xway";
 			reg = <0xe100bb0 0x40>;
 			#gpio-cells = <2>;
 			gpio-controller;

 			lantiq,shadow = <0xffffff>;
 			lantiq,groups = <0x7>;
 			lantiq,dsl = <0x0>;
 			lantiq,phy1 = <0x0>;
 			lantiq,phy2 = <0x0>;
 		};

 		deu@e103100 {
 			status = "disabled";
 			compatible = "lantiq,deu-xrx200";
 			reg = <0xe103100 0xf00>;

 			/* supported by upstream? */
 			lantiq,algo = "aes", "des", "arc4", "sha1", "md5", "sha1-hmac", "md5-hmac";
 			lantiq,dma-mode = <0>;
 			lantiq,sync-mode = <1>;
 		};

 		dma0: dma@e104100 {
 			compatible = "lantiq,dma-xway";
 			reg = <0xe104100 0x800>;
 			interrupt-parent = <&icu0>;
 			interrupts = <72 73 74 75 76 77 78 79 80 81 82 83 97 98 99 100 101 70 88 93 136 137 138 139>;
 			lantiq,desc-num = <256>;
 			lantiq,dma-hw-poll = <1>;
 			lantiq,dma-pkt-arb = <0>;
 		};

 		ebu0: ebu@6000000 {
 			compatible = "lantiq,ebu-xway";
 			reg = <0x6000000 0x100>,
 				<0x6000100 0x100>;
 		};

 		usb@e101000 {
 			status = "disabled";
 			compatible = "lantiq,xrx200-usb";
 			reg = <0xe101000 0x1000
 				0xe120000 0x3f000>;
 			interrupt-parent = <&icu0>;
 			interrupts = <62 91>;
 			dr_mode = "host";
 			phys = <&usb_phy0>;
 			phy-names = "usb2-phy";
 		};

 		usb1: usb@e106000 {
 			status = "disabled";
 			compatible = "lantiq,xrx200-usb";
 			reg = <0xe106000 0x1000>;
 			interrupt-parent = <&icu0>;
 			interrupts = <91>;
 			dr_mode = "host";
 			phys = <&usb_phy1>;
 			phy-names = "usb2-phy";
 		};

 		eth0: eth@e108000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "lantiq,xrx200-net";
 			reg = < 0xe108000 0x3000 /* switch */
 				0xe10b100 0x70 /* mdio */
 				0xe10b1d8 0x30 /* mii */
 				0xe10b308 0x30 /* pmac */
 			>;
 			interrupt-parent = <&icu0>;
 			interrupts = <75 73 72>;
 			resets = <&reset0 21 16>, <&reset0 8 8>;
 			reset-names = "switch", "ppe";
 			lantiq,phys = <&gphy0>, <&gphy1>, <&gphy2>;
 		};

 		mei@e116000 {
 			compatible = "lantiq,mei-xrx300";
 			reg = <0xe116000 0x100>;
 			interrupt-parent = <&icu0>;
 			interrupts = <63 61>;
 		};

 		ppe@e234000 {
 			compatible = "lantiq,ppe-xrx200";
 			interrupt-parent = <&icu0>;
 			interrupts = <32 95 69>;
 		};

 		wlan@a000000 {
 			compatible ="lantiq,wlan-xrx330";
 			status = "okay";
 			interrupt-parent = <&icu0>;
 			interrupts = <26>;
 		};

 		pcie0: pcie@d900000 {
 			status = "disabled";
 			compatible = "lantiq,pcie-xrx330";
 			device_type = "pci";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			reg = < 0xD900000 0x1000 /* RC controller */
 				0xD000000 0x800000 /* Cfg Space */
 				0xE100900 0x100 /* App logic */
 				0xF106800 0x200 /* PCIe PHY Reg */
 				0xF600000 0x100000 /* MSI addr space */
 				0xF700000 0x400 /* MSI PIC */
 			>;
 			reg-names = "csr", "cfg", "app", "phy", "msi", "pic";
 			interrupt-parent = <&icu0>;
 			interrupts = <163 164 165 38 161>;
 			interrupt-names = "msi0", "msi1", "msi2", "msi3", "ir";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &icu0  144>,
 					<0 0 0 2 &icu0  145>,
 					<0 0 0 3 &icu0  146>,
 					<0 0 0 4 &icu0  147>;
 			ranges = <0x02000000 0 0x0C000000 0x0C000000 0 0x01000000    /* Non-pretechable memory 32bit */
 				  0x01000000 0 0x0D800000 0x0D800000 0 0x00100000    /* Downsream I/O */
 				 >;
 			resets = <&rcu0 12>,
 				 <&rcu0 22>;
 			reset-names = "phy", "core";
 			lantiq,inbound-shift = <12>;
 			lantiq,outbound-shift = <4>;
 		};

 		pcie1: pcie@9900000 {
 			status = "disabled";
 			compatible = "lantiq,pcie-xrx330";
 			device_type = "pci";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			reg = < 0x9900000 0x1000 /* RC controller */
 				0x9000000 0x800000 /* Cfg Space */
 				0xE100700 0x100 /* App logic */
 				0xF700400 0x200 /* PCIe PHY Reg */
 				0xF400000 0x100000 /* MSI addr space */
 				0xF500000 0x400 /* MSI PIC */
 			>;
 			reg-names = "csr", "cfg", "app", "phy", "msi", "pic";
 			interrupt-parent = <&icu0>;
 			interrupts = <49 50 51 52 57>;
 			interrupt-names = "msi0", "msi1", "msi2", "msi3", "ir";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &icu0  17>,
 					<0 0 0 2 &icu0  18>,
 					<0 0 0 3 &icu0  19>,
 					<0 0 0 4 &icu0  20>;
 			bus-range = <0x00 0xff>;
 			ranges = < 0x02000000 0 0x08000000 0x08000000 0 0x01000000    /* Non-pretechable memory 32bit */
 				   0x01000000 0 0x09800000 0x09800000 0 0x00100000    /* Downsream I/O */
 				 >;
 			resets = <&rcu0 13>,
 				 <&rcu0 27>;
 			reset-names = "phy", "core";
 			lantiq,inbound-shift = <13>;
 			lantiq,outbound-shift = <8>;
 		};

 		pcie2: pcie@9B00000 {
 			status = "disabled";
 			compatible = "lantiq,pcie-xrx330";
 			device_type = "pci";
 			#address-cells = <3>;
 			#size-cells = <2>;
 			reg = < 0x9B00000 0x1000 /* RC controller */
 				0xA800000 0x800000 /* Cfg Space */
 				0xE100400 0x100 /* App logic */
 				0xF106A00 0x200 /* PCIe PHY Reg */
 				0xF700A00 0x100000 /* MSI addr space */
 				0xF700600 0x400 /* MSI PIC */
 			>;
 			reg-names = "csr", "cfg", "app", "phy", "msi", "pic";
 			interrupt-parent = <&icu0>;
 			interrupts = <84 85 86 87 61>;
 			interrupt-names = "msi0", "msi1", "msi2", "msi3", "ir";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &icu0  27>,
 					<0 0 0 2 &icu0  71>,
 					<0 0 0 3 &icu0  89>,
 					<0 0 0 4 &icu0  90>;
 			bus-range = <0x00 0xff>;
 			ranges = < 0x02000000 0 0x0B000000 0x0B000000 0 0x01000000    /* Non-pretechable memory 32bit */
 				   0x01000000 0 0x09A00000 0x09A00000 0 0x00100000    /* Downsream I/O */
 				 >;
 			resets = <&rcu0 60>,
 				 <&rcu0 61>;
 			reset-names = "phy", "core";
 			lantiq,inbound-shift = <14>;
 			lantiq,outbound-shift = <17>;
 		};

 	};

};
Martin Blumenstingl via openwrt-devel Sept. 4, 2019, 4:48 p.m. UTC | #7
The sender domain has a DMARC Reject/Quarantine policy which disallows
sending mailing list messages using the original "From" header.

To mitigate this problem, the original message has been wrapped
automatically by the mailing list software.
Hi Enrico,

On Wed, Sep 4, 2019 at 12:07 PM Enrico Mioso <mrkiko.rs@gmail.com> wrote:
>
> Hi there!
>
> So I am trying to get ethernet working on this AR10 device.
> It has 3 GPHYs:
>
>                         gphy0: gphy@20 {
>                                 compatible = "lantiq,xrx300-gphy";
>                                 reg = <0x20 0x4>;
>
>                                 resets = <&reset0 31 30>, <&reset1 7 7>;
>                                 reset-names = "gphy", "gphy2";
>                         };
>
>                         gphy1: gphy@58 {
>                                 compatible = "lantiq,xrx300-gphy";
>                                 reg = <0x58 0x4>;
>
>                                 resets = <&reset0 29 28>, <&reset1 6 6>;
>                                 reset-names = "gphy", "gphy2";
>                         };
>
>                         gphy2: gphy@ac {
>                                 compatible = "lantiq,xrx300-gphy";
>                                 reg = <0xac 0x4>;
>                                 resets = <&reset0 27 26>, <&reset1 5 5>;
>                                 reset-names = "gphy", "gphy2";
>                         };
>
> And firmware load addresses for GPHYs are correct as per the vendor code:
> #define IFX_RCU_GPHY0_FW_ADDR                   ((volatile u32*)(IFX_RCU + 0x0020))
> #define IFX_RCU_GPHY1_FW_ADDR                   ((volatile u32*)(IFX_RCU + 0x0058))
> #define IFX_RCU_GPHY2_FW_ADDR                   ((volatile u32*)(IFX_RCU + 0x00AC))
the register part of your .dts looks fine based on this

> But driver was failing to initialize due to missing clock gates.
> In sysctrl.c, we have:
> clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY); // OK for GPHY0
> clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY); //problem for GPHY1
>
> And GPHY2?
the UGW kernel documents all the PMUs in
drivers/char/ifxmips_pmu_SOC.h, in your case that is:
drivers/char/ifxmips_pmu_ar10.h [0]
I don't remember how to translate that file to an English sentence but
you can figure it out on your own (for example by comparing the vr9
sysctrl.c code with

resets are found in the same directory but a different file: ifxmips_rcu_ar10.h

(sorry for the short answer but I have to leave in a few minutes)


happy hacking!
Martin


[0] https://github.com/uwehermann/easybox-904-xdsl-firmware/blob/master/linux/linux-2.6.32.32/drivers/char/ifxmips_pmu_ar10.h
Hauke Mehrtens Sept. 4, 2019, 5:12 p.m. UTC | #8
Hi Enrico,


On 9/4/19 6:48 PM, Martin Blumenstingl wrote:
> Hi Enrico,
> 
> On Wed, Sep 4, 2019 at 12:07 PM Enrico Mioso <mrkiko.rs@gmail.com> wrote:
>>
>> Hi there!
>>
>> So I am trying to get ethernet working on this AR10 device.
>> It has 3 GPHYs:

I did some fixes for the reset bits,, the rest is ok.

>>
>>                         gphy0: gphy@20 {
>>                                 compatible = "lantiq,xrx300-gphy";
>>                                 reg = <0x20 0x4>;
>>
>>                                 resets = <&reset0 31 30>, <&reset1 7 7>;
resets = <&reset0 31 30>, <&reset1 6 6>;
>>                                 reset-names = "gphy", "gphy2";
>>                         };
>>
>>                         gphy1: gphy@58 {
>>                                 compatible = "lantiq,xrx300-gphy";
>>                                 reg = <0x58 0x4>;
>>
>>                                 resets = <&reset0 29 28>, <&reset1 6 6>;
resets = <&reset0 29 28>, <&reset1 7 7>;
>>                                 reset-names = "gphy", "gphy2";
>>                         };
>>
>>                         gphy2: gphy@ac {
>>                                 compatible = "lantiq,xrx300-gphy";
>>                                 reg = <0xac 0x4>;
>>                                 resets = <&reset0 27 26>, <&reset1 5 5>;
resets = <&reset0 28 13>, <&reset1 8 8>;
>>                                 reset-names = "gphy", "gphy2";
>>                         };
>>
>> And firmware load addresses for GPHYs are correct as per the vendor code:
>> #define IFX_RCU_GPHY0_FW_ADDR                   ((volatile u32*)(IFX_RCU + 0x0020))
>> #define IFX_RCU_GPHY1_FW_ADDR                   ((volatile u32*)(IFX_RCU + 0x0058))
>> #define IFX_RCU_GPHY2_FW_ADDR                   ((volatile u32*)(IFX_RCU + 0x00AC))
> the register part of your .dts looks fine based on this
> 
>> But driver was failing to initialize due to missing clock gates.
>> In sysctrl.c, we have:
>> clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY); // OK for GPHY0
>> clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY); //problem for GPHY1
>>
>> And GPHY2?
> the UGW kernel documents all the PMUs in
> drivers/char/ifxmips_pmu_SOC.h, in your case that is:
> drivers/char/ifxmips_pmu_ar10.h [0]
> I don't remember how to translate that file to an English sentence but
> you can figure it out on your own (for example by comparing the vr9
> sysctrl.c code with
> 
> resets are found in the same directory but a different file: ifxmips_rcu_ar10.h
> 
> (sorry for the short answer but I have to leave in a few minutes)

Be aware that the GPHYs are connected to different ports of the GSWIP
compared to the VR9. With the upstream DSA driver you should be able to
define this mostly in device tree.

GMAC0: RGMII port
GMAC2: GPHY0 (GMII)
GMAC3: GPHY0 (MII)
GMAC4: GPHY1 (GMII)
GMAC5: GPHY1 (MII) or RGMII port
GMAC1: GPHY2 (GMII)

Hauke
Mathias Kresin Sept. 5, 2019, 6:10 a.m. UTC | #9
04/09/2019 12:07, Enrico Mioso:
> Hi there!
> 
> So I am trying to get ethernet working on this AR10 device.
> It has 3 GPHYs:
> 
>              gphy0: gphy@20 {
>                  compatible = "lantiq,xrx300-gphy";
>                  reg = <0x20 0x4>;
> 
>                  resets = <&reset0 31 30>, <&reset1 7 7>;
>                  reset-names = "gphy", "gphy2";
>              };
> 
>              gphy1: gphy@58 {
>                  compatible = "lantiq,xrx300-gphy";
>                  reg = <0x58 0x4>;
> 
>                  resets = <&reset0 29 28>, <&reset1 6 6>;
>                  reset-names = "gphy", "gphy2";
>              };
> 
>              gphy2: gphy@ac {
>                  compatible = "lantiq,xrx300-gphy";
>                  reg = <0xac 0x4>;
>                  resets = <&reset0 27 26>, <&reset1 5 5>;
>                  reset-names = "gphy", "gphy2";
>              };
> 
> And firmware load addresses for GPHYs are correct as per the vendor code:
> #define IFX_RCU_GPHY0_FW_ADDR                   ((volatile u32*)(IFX_RCU 
> + 0x0020))
> #define IFX_RCU_GPHY1_FW_ADDR                   ((volatile u32*)(IFX_RCU 
> + 0x0058))
> #define IFX_RCU_GPHY2_FW_ADDR                   ((volatile u32*)(IFX_RCU 
> + 0x00AC))
> 
> But driver was failing to initialize due to missing clock gates.
> In sysctrl.c, we have:
> clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY); // OK for GPHY0
> clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY); //problem for GPHY1

The first parameter of clkdev_add_pmu doesn't match your dts. It has to 
be "1f203058.gphy"

Regards
Mathias
Enrico Mioso Sept. 5, 2019, 7:49 a.m. UTC | #10
On Thu, 5 Sep 2019, Mathias Kresin wrote:
...

>> In sysctrl.c, we have:
>> clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY); // OK for GPHY0
>> clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY); //problem for GPHY1

> The first parameter of clkdev_add_pmu doesn't match your dts. It has to be 
> "1f203058.gphy"
>
> Regards
> Mathias
>
thank you very much Mathias.
Yeah - infact I did this change, resulting in the first two GPHYs initializing, while the one at "1f2030ac.gphy" had more issues - and kernel oopsed.
So I was thinking the logic was wrong. I'll look at it again.

Enrico

Patch
diff mbox series

diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index c7f6dee..b30fdcc 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -165,7 +165,7 @@  void ltq_pmu_enable(unsigned int module)
  	spin_unlock(&g_pmu_lock);

  	if (!retry)
-		panic("activating PMU module failed!");
+		panic("activating PMU module %u failed!",module);
  }
  EXPORT_SYMBOL(ltq_pmu_enable);

@@ -180,7 +180,7 @@  void ltq_pmu_disable(unsigned int module)
  	spin_unlock(&g_pmu_lock);

  	if (!retry)
-		pr_warn("deactivating PMU module failed!");
+		pr_warn("deactivating PMU module %u failed!",module);
  }
  EXPORT_SYMBOL(ltq_pmu_disable);

@@ -218,7 +218,7 @@  static int pmu_enable(struct clk *clk)
  	}

  	if (!retry)
-		panic("activating PMU module failed!");
+		panic("activating PMU module %u (clock gate) failed!",clk->module);

  	return 0;
  }
@@ -243,7 +243,7 @@  static void pmu_disable(struct clk *clk)
  	}

  	if (!retry)
-		pr_warn("deactivating PMU module failed!");
+		pr_warn("deactivating PMU module %u (clock gate) failed!",clk->module);
  }

  static void usb_set_clock(void)