From patchwork Thu Aug 29 22:47:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Reddy X-Patchwork-Id: 1155546 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="sFRAwo2e"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46KHlS4nQ1z9sNf for ; Fri, 30 Aug 2019 08:46:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728345AbfH2Wpo (ORCPT ); Thu, 29 Aug 2019 18:45:44 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:17659 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728243AbfH2Wpn (ORCPT ); Thu, 29 Aug 2019 18:45:43 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 29 Aug 2019 15:45:43 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 29 Aug 2019 15:45:42 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 29 Aug 2019 15:45:42 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 29 Aug 2019 22:45:42 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 29 Aug 2019 22:45:42 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 29 Aug 2019 22:45:42 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 29 Aug 2019 15:45:42 -0700 From: Krishna Reddy CC: , , , , , , , , , , , , , , Krishna Reddy Subject: [PATCH 2/7] dt-bindings: arm-smmu: Add binding for nvidia,smmu-v2 Date: Thu, 29 Aug 2019 15:47:02 -0700 Message-ID: <1567118827-26358-3-git-send-email-vdumpa@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1567118827-26358-1-git-send-email-vdumpa@nvidia.com> References: <1567118827-26358-1-git-send-email-vdumpa@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1567118743; bh=Z+8xf1MWME35eRIyHuj/Q0XxVKgnVmKXg4fYXe2zY4A=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=sFRAwo2eNHp8AFaRvCDp3B1gmqL5DauwFGVnEw7OoOiUgEBpR0zK6OO6r7G6+8gzZ NMzIsSVhu4OJvpsx+KNdacvkk4FMnUaNSAtsMecoFKKvmN5XYjXML9GKKAnuyq5xSO 3Njk4gSi6G6hI4X/OhdLyyz1kktg6zPVcpemfa721saCkNh37XKOiLLwQ5RPH3Y90v WD3VXxmQdVMplH4rJwhUxuQ+XJy5olfFQEe9BpsQ6FJ/TGXcaVaPb81nSI7Dgr/zbq F4bg9+GXpRL9/5zJuuCxwwSrwrBX85p/Pf08cV4kfV022ztMohOt5pFt6p36lCX99x FIo5TKWqEbkdw== To: unlisted-recipients:; (no To-header on input) Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add binding doc for Nvidia's smmu-v2 implementation. Signed-off-by: Krishna Reddy --- Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 3133f3b..0de3759 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -17,6 +17,7 @@ conditions. "arm,mmu-401" "arm,mmu-500" "cavium,smmu-v2" + "nidia,smmu-v2" "qcom,smmu-v2" depending on the particular implementation and/or the