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[217.229.24.144]) by smtp.gmail.com with ESMTPSA id d21sm670705edv.57.2019.08.29.15.19.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 15:19:19 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Nagarjuna Kristam , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/7] soc/tegra: fuse: Add cell information Date: Fri, 30 Aug 2019 00:19:07 +0200 Message-Id: <20190829221911.24876-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190829221911.24876-1-thierry.reding@gmail.com> References: <20190829221911.24876-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding Create nvmem cells for all the fuses currently used by consumers. Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 90 +++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 3ce2138b278b..c6c6a7746046 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -86,6 +86,94 @@ static int tegra_fuse_read(void *priv, unsigned int offset, void *value, return 0; } +static const struct nvmem_cell_info tegra_fuse_cells[] = { + { + .name = "tsensor-cpu1", + .offset = 0x084, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-cpu2", + .offset = 0x088, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-cpu0", + .offset = 0x098, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "xusb-pad-calibration", + .offset = 0x0f0, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-cpu3", + .offset = 0x12c, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "sata-calibration", + .offset = 0x124, + .bytes = 1, + .bit_offset = 0, + .nbits = 2, + }, { + .name = "tsensor-gpu", + .offset = 0x154, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-mem0", + .offset = 0x158, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-mem1", + .offset = 0x15c, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-pllx", + .offset = 0x160, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-common", + .offset = 0x180, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "tsensor-realignment", + .offset = 0x1fc, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "gpu-calibration", + .offset = 0x204, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "xusb-pad-calibration-ext", + .offset = 0x250, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, +}; + static int tegra_fuse_probe(struct platform_device *pdev) { void __iomem *base = fuse->base; @@ -127,6 +215,8 @@ static int tegra_fuse_probe(struct platform_device *pdev) nvmem.name = "fuse"; nvmem.id = -1; nvmem.owner = THIS_MODULE; + nvmem.cells = tegra_fuse_cells; + nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells); nvmem.type = NVMEM_TYPE_OTP; nvmem.read_only = true; nvmem.root_only = true;