From patchwork Tue Sep 20 12:49:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 115525 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2A7B4B70D1 for ; Tue, 20 Sep 2011 22:50:19 +1000 (EST) Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R5zlk-0006qX-OP; Tue, 20 Sep 2011 12:49:49 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1R5zlk-00056v-AC; Tue, 20 Sep 2011 12:49:48 +0000 Received: from metis.ext.pengutronix.de ([2001:6f8:1178:4:290:27ff:fe1d:cc33]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R5zlO-00052m-Ex for linux-arm-kernel@lists.infradead.org; Tue, 20 Sep 2011 12:49:27 +0000 Received: from octopus.hi.pengutronix.de ([2001:6f8:1178:2:215:17ff:fe12:23b0]) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1R5zlK-0006AZ-Ae; Tue, 20 Sep 2011 14:49:22 +0200 Received: from sha by octopus.hi.pengutronix.de with local (Exim 4.76) (envelope-from ) id 1R5zlK-0008Aq-37; Tue, 20 Sep 2011 14:49:22 +0200 From: Sascha Hauer To: Subject: [PATCH 4/4] ARM i.MX entry-macro.S: remove now unused code Date: Tue, 20 Sep 2011 14:49:16 +0200 Message-Id: <1316522956-28530-5-git-send-email-s.hauer@pengutronix.de> X-Mailer: git-send-email 1.7.6.3 In-Reply-To: <1316522956-28530-1-git-send-email-s.hauer@pengutronix.de> References: <1316522956-28530-1-git-send-email-s.hauer@pengutronix.de> X-SA-Exim-Connect-IP: 2001:6f8:1178:2:215:17ff:fe12:23b0 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110920_084926_952596_FA7607AE X-CRM114-Status: GOOD ( 17.49 ) X-Spam-Score: -0.5 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.5 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Sascha Hauer , Shawn Guo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/entry-macro.S | 58 +------------------------- 1 files changed, 1 insertions(+), 57 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index 066d464..842fbcb 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -9,72 +9,16 @@ * published by the Free Software Foundation. */ -#include +/* Unused, we use CONFIG_MULTI_IRQ_HANDLER */ -#define AVIC_NIMASK 0x04 - - @ this macro disables fast irq (not implemented) .macro disable_fiq .endm .macro get_irqnr_preamble, base, tmp -#ifndef CONFIG_MXC_TZIC - ldr \base, =avic_base - ldr \base, [\base] -#ifdef CONFIG_MXC_IRQ_PRIOR - ldr r4, [\base, #AVIC_NIMASK] -#endif -#elif defined CONFIG_MXC_TZIC - ldr \base, =tzic_base - ldr \base, [\base] -#endif /* CONFIG_MXC_TZIC */ .endm .macro arch_ret_to_user, tmp1, tmp2 .endm - @ this macro checks which interrupt occurred - @ and returns its number in irqnr - @ and returns if an interrupt occurred in irqstat .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -#ifndef CONFIG_MXC_TZIC - @ Load offset & priority of the highest priority - @ interrupt pending from AVIC_NIVECSR - ldr \irqstat, [\base, #0x40] - @ Shift to get the decoded IRQ number, using ASR so - @ 'no interrupt pending' becomes 0xffffffff - mov \irqnr, \irqstat, asr #16 - @ set zero flag if IRQ + 1 == 0 - adds \tmp, \irqnr, #1 -#ifdef CONFIG_MXC_IRQ_PRIOR - bicne \tmp, \irqstat, #0xFFFFFFE0 - strne \tmp, [\base, #AVIC_NIMASK] - streq r4, [\base, #AVIC_NIMASK] -#endif -#elif defined CONFIG_MXC_TZIC - @ Load offset & priority of the highest priority - @ interrupt pending. - @ 0x080 is INTSEC0 register - @ 0xD80 is HIPND0 register - mov \irqnr, #0 -1000: add \irqstat, \base, \irqnr, lsr #3 - ldr \tmp, [\irqstat, #0xd80] - ldr \irqstat, [\irqstat, #0x080] - ands \tmp, \tmp, \irqstat - bne 1001f - add \irqnr, \irqnr, #32 - cmp \irqnr, #128 - blo 1000b - b 2001f -1001: mov \irqstat, #1 -1002: tst \tmp, \irqstat - bne 2002f - movs \tmp, \tmp, lsr #1 - addne \irqnr, \irqnr, #1 - bne 1002b -2001: - mov \irqnr, #0 -2002: - movs \irqnr, \irqnr -#endif .endm