| Message ID | 1566995328-15158-9-git-send-email-henryc.chen@mediatek.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Add driver for dvfsrc, support for active state of scpsys | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Wed, Aug 28, 2019 at 08:28:46PM +0800, Henry Chen wrote: > Add interconnect provider dt-bindings for MT8183. > > Signed-off-by: Henry Chen <henryc.chen@mediatek.com> > --- > .../devicetree/bindings/soc/mediatek/dvfsrc.txt | 9 +++++++++ > include/dt-bindings/interconnect/mtk,mt8183-emi.h | 18 ++++++++++++++++++ > 2 files changed, 27 insertions(+) > create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h > > diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > index 7f43499..da98ec9 100644 > --- a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > @@ -12,6 +12,11 @@ Required Properties: > - clock-names: Must include the following entries: > "dvfsrc": DVFSRC module clock > - clocks: Must contain an entry for each entry in clock-names. > +- #interconnect-cells : should contain 1 > +- interconnect : interconnect providers support dram bandwidth requirements. > + The provider is able to communicate with the DVFSRC and send the dram > + bandwidth to it. shall contain only one of the following: > + "mediatek,mt8183-emi" > > Example: > > @@ -20,4 +25,8 @@ Example: > reg = <0 0x10012000 0 0x1000>; > clocks = <&infracfg CLK_INFRA_DVFSRC>; > clock-names = "dvfsrc"; > + ddr_emi: interconnect { The EMI is a sub-module in the DVFSRC? This is the DDR controller or something else? > + compatible = "mediatek,mt8183-emi"; > + #interconnect-cells = <1>; > + }; > };
On Mon, 2019-09-02 at 14:38 +0100, Rob Herring wrote: Hi Rob, > On Wed, Aug 28, 2019 at 08:28:46PM +0800, Henry Chen wrote: > > Add interconnect provider dt-bindings for MT8183. > > > > Signed-off-by: Henry Chen <henryc.chen@mediatek.com> > > --- > > .../devicetree/bindings/soc/mediatek/dvfsrc.txt | 9 +++++++++ > > include/dt-bindings/interconnect/mtk,mt8183-emi.h | 18 ++++++++++++++++++ > > 2 files changed, 27 insertions(+) > > create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h > > > > diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > > index 7f43499..da98ec9 100644 > > --- a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > > +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt > > @@ -12,6 +12,11 @@ Required Properties: > > - clock-names: Must include the following entries: > > "dvfsrc": DVFSRC module clock > > - clocks: Must contain an entry for each entry in clock-names. > > +- #interconnect-cells : should contain 1 > > +- interconnect : interconnect providers support dram bandwidth requirements. > > + The provider is able to communicate with the DVFSRC and send the dram > > + bandwidth to it. shall contain only one of the following: > > + "mediatek,mt8183-emi" > > > > Example: > > > > @@ -20,4 +25,8 @@ Example: > > reg = <0 0x10012000 0 0x1000>; > > clocks = <&infracfg CLK_INFRA_DVFSRC>; > > clock-names = "dvfsrc"; > > + ddr_emi: interconnect { > > The EMI is a sub-module in the DVFSRC? This is the DDR controller or > something else? Yes, EMI is a sub-module in the DVFSRC, the EMI through interconnect framework to collect DRAM bandwidth from other device drivers and will send the bandwidth result to DVFSRC driver. > > > > + compatible = "mediatek,mt8183-emi"; > > + #interconnect-cells = <1>; > > + }; > > }; >
diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt index 7f43499..da98ec9 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt @@ -12,6 +12,11 @@ Required Properties: - clock-names: Must include the following entries: "dvfsrc": DVFSRC module clock - clocks: Must contain an entry for each entry in clock-names. +- #interconnect-cells : should contain 1 +- interconnect : interconnect providers support dram bandwidth requirements. + The provider is able to communicate with the DVFSRC and send the dram + bandwidth to it. shall contain only one of the following: + "mediatek,mt8183-emi" Example: @@ -20,4 +25,8 @@ Example: reg = <0 0x10012000 0 0x1000>; clocks = <&infracfg CLK_INFRA_DVFSRC>; clock-names = "dvfsrc"; + ddr_emi: interconnect { + compatible = "mediatek,mt8183-emi"; + #interconnect-cells = <1>; + }; }; diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h b/include/dt-bindings/interconnect/mtk,mt8183-emi.h new file mode 100644 index 0000000..2a54856 --- /dev/null +++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H +#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H + +#define MT8183_SLAVE_DDR_EMI 0 +#define MT8183_MASTER_MCUSYS 1 +#define MT8183_MASTER_GPU 2 +#define MT8183_MASTER_MMSYS 3 +#define MT8183_MASTER_MM_VPU 4 +#define MT8183_MASTER_MM_DISP 5 +#define MT8183_MASTER_MM_VDEC 6 +#define MT8183_MASTER_MM_VENC 7 +#define MT8183_MASTER_MM_CAM 8 +#define MT8183_MASTER_MM_IMG 9 +#define MT8183_MASTER_MM_MDP 10 + +#endif
Add interconnect provider dt-bindings for MT8183. Signed-off-by: Henry Chen <henryc.chen@mediatek.com> --- .../devicetree/bindings/soc/mediatek/dvfsrc.txt | 9 +++++++++ include/dt-bindings/interconnect/mtk,mt8183-emi.h | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h