Message ID | 20190827033145.20038-1-Zhiqiang.Hou@nxp.com |
---|---|
State | Accepted |
Commit | c9ba88bafc786a258f64ce673fc63b9e5994c88a |
Delegated to: | Priyanka Jain |
Headers | show |
Series | [U-Boot,PATCHv3] armv8: fsl-layerscape: Fix a typo of Layerscape PCIe config entry | expand |
>-----Original Message----- >From: Z.q. Hou >Sent: Tuesday, August 27, 2019 9:00 AM >To: u-boot@lists.denx.de; Prabhakar Kushwaha ><prabhakar.kushwaha@nxp.com>; alexm.osslist@gmail.com; >bmeng.cn@gmail.com >Cc: Z.q. Hou <zhiqiang.hou@nxp.com> >Subject: [PATCHv3] armv8: fsl-layerscape: Fix a typo of Layerscape PCIe config >entry > >From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > >The correct config entry is CONFIG_PCIE_LAYERSCAPE and this typo results in >skipping the fixup of Linux PCIe DT nodes. > >Also enable the fixup when Layerscape Gen4 controller driver is enabled. > >Fixes: 4da0e52c9dc0 (armv8: fsl-layerscape: fix config dependency for >layerscape pci code) >Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> >Reviewed-by: Bin Meng <bmeng.cn@gmail.com[] > Applied to fsl-qoriq master, awaiting upstream. Thanks priyankajain
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index fabe0f0359..25b7afe064 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -435,7 +435,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); -#ifdef CONFIG_PCI_LAYERSCAPE +#if defined(CONFIG_PCIE_LAYERSCAPE) || defined(CONFIG_PCIE_LAYERSCAPE_GEN4) ft_pci_setup(blob, bd); #endif