| Message ID | 20190825154423.30781-4-Zhiqiang.Hou@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | Prabhakar Kushwaha |
| Headers | show |
| Series | dm: pcie_fsl: Fix some issues | expand |
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote: > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > The PCIe controller register address in CCSR is different > on various platforms, the current code erroneously use > the hardcoded address (0xffe240000) and stride (0x10000) > to calculate the controller's index. > > Fix it by adding the related info to the driver data > structure. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > --- > V2: > - No change. > > drivers/pci/pcie_fsl.c | 14 ++++++++++++-- > drivers/pci/pcie_fsl.h | 7 +++++++ > 2 files changed, 19 insertions(+), 2 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Hi Bin, Thanks a lot for your review! Regards, Zhiqiang > -----Original Message----- > From: Bin Meng <bmeng.cn@gmail.com> > Sent: 2019年8月26日 14:11 > To: Z.q. Hou <zhiqiang.hou@nxp.com> > Cc: u-boot@lists.denx.de; Prabhakar Kushwaha > <prabhakar.kushwaha@nxp.com> > Subject: Re: [PATCHv2 3/3] dm: pcie_fsl: Fix the calculation of controller > index > > On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote: > > > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > The PCIe controller register address in CCSR is different on various > > platforms, the current code erroneously use the hardcoded address > > (0xffe240000) and stride (0x10000) to calculate the controller's > > index. > > > > Fix it by adding the related info to the driver data structure. > > > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > --- > > V2: > > - No change. > > > > drivers/pci/pcie_fsl.c | 14 ++++++++++++-- drivers/pci/pcie_fsl.h | > > 7 +++++++ > > 2 files changed, 19 insertions(+), 2 deletions(-) > > > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 60d274124b..ff9b07506a 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -579,6 +579,7 @@ static int fsl_pcie_probe(struct udevice *dev) static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) { struct fsl_pcie *pcie = dev_get_priv(dev); + struct fsl_pcie_data *info; int ret; pcie->regs = dev_remap_addr(dev); @@ -593,7 +594,10 @@ static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) return ret; } - pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000; + info = (struct fsl_pcie_data *)dev_get_driver_data(dev); + pcie->info = info; + pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) - + info->block_offset) / info->stride; return 0; } @@ -603,8 +607,14 @@ static const struct dm_pci_ops fsl_pcie_ops = { .write_config = fsl_pcie_write_config, }; +static struct fsl_pcie_data t2080_data = { + .block_offset = 0x240000, + .block_offset_mask = 0x3fffff, + .stride = 0x10000, +}; + static const struct udevice_id fsl_pcie_ids[] = { - { .compatible = "fsl,pcie-t2080" }, + { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, { } }; diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index cdf28dbea2..32af54ce49 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -45,6 +45,12 @@ #define P4080_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA000) +struct fsl_pcie_data { + u32 block_offset; /* Offset from CCSR of 1st controller */ + u32 block_offset_mask; /* Mask out the CCSR base */ + u32 stride; /* Offset stride between controllers */ +}; + struct fsl_pcie { int idx; struct udevice *bus; @@ -54,6 +60,7 @@ struct fsl_pcie { bool mode; /* RC&EP mode flag */ bool enabled; /* Enable status */ struct list_head list; + struct fsl_pcie_data *info; }; extern struct list_head fsl_pcie_list;