| Message ID | f6ee7d33103b43b2f1e1331c23c36057ef20b20d.1566542697.git.chunfeng.yun@mediatek.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [01/11] dt-bindings: phy-mtk-tphy: add two optional properties for u2phy | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success |
On Fri, Aug 23, 2019 at 03:00:11PM +0800, Chunfeng Yun wrote: > Usually the digital and anolog phys use the same reference clock, > but on some platforms, they are separated, so add another optional > clock to support it. > In order to keep the clock names consistent with PHY IP's, use > the da_ref for anolog phy and ref clock for digital phy. > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > --- > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > index dbc143ed5999..ed9a2641f204 100644 > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > @@ -41,9 +41,12 @@ Optional properties (PHY_TYPE_USB2 port (child) node): > - clocks : a list of phandle + clock-specifier pairs, one for each > entry in clock-names > - clock-names : may contain > - "ref": 48M reference clock for HighSpeed anolog phy; and 26M > - reference clock for SuperSpeed anolog phy, sometimes is > + "ref": 48M reference clock for HighSpeed (digital) phy; and 26M > + reference clock for SuperSpeed (digital) phy, sometimes is > 24M, 25M or 27M, depended on platform. > + "da_ref": the reference clock of anolog phy, used if the clocks > + of anolog and digital phys are separated, otherwise uses s/amolog/analog/ > + "ref" clock only if need. needed. > > - mediatek,eye-src : u32, the value of slew rate calibrate > - mediatek,eye-vrt : u32, the selection of VRT reference voltage > -- > 2.23.0 >
On Thu, 2019-08-29 at 15:05 -0500, Rob Herring wrote: > On Fri, Aug 23, 2019 at 03:00:11PM +0800, Chunfeng Yun wrote: > > Usually the digital and anolog phys use the same reference clock, > > but on some platforms, they are separated, so add another optional > > clock to support it. > > In order to keep the clock names consistent with PHY IP's, use > > the da_ref for anolog phy and ref clock for digital phy. > > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > > --- > > Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 7 +++++-- > > 1 file changed, 5 insertions(+), 2 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > index dbc143ed5999..ed9a2641f204 100644 > > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt > > @@ -41,9 +41,12 @@ Optional properties (PHY_TYPE_USB2 port (child) node): > > - clocks : a list of phandle + clock-specifier pairs, one for each > > entry in clock-names > > - clock-names : may contain > > - "ref": 48M reference clock for HighSpeed anolog phy; and 26M > > - reference clock for SuperSpeed anolog phy, sometimes is > > + "ref": 48M reference clock for HighSpeed (digital) phy; and 26M > > + reference clock for SuperSpeed (digital) phy, sometimes is > > 24M, 25M or 27M, depended on platform. > > + "da_ref": the reference clock of anolog phy, used if the clocks > > + of anolog and digital phys are separated, otherwise uses > > s/amolog/analog/ will fix it > > > + "ref" clock only if need. > > needed. also here Thanks a lot > > > > > - mediatek,eye-src : u32, the value of slew rate calibrate > > - mediatek,eye-vrt : u32, the selection of VRT reference voltage > > -- > > 2.23.0 > >
diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index dbc143ed5999..ed9a2641f204 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -41,9 +41,12 @@ Optional properties (PHY_TYPE_USB2 port (child) node): - clocks : a list of phandle + clock-specifier pairs, one for each entry in clock-names - clock-names : may contain - "ref": 48M reference clock for HighSpeed anolog phy; and 26M - reference clock for SuperSpeed anolog phy, sometimes is + "ref": 48M reference clock for HighSpeed (digital) phy; and 26M + reference clock for SuperSpeed (digital) phy, sometimes is 24M, 25M or 27M, depended on platform. + "da_ref": the reference clock of anolog phy, used if the clocks + of anolog and digital phys are separated, otherwise uses + "ref" clock only if need. - mediatek,eye-src : u32, the value of slew rate calibrate - mediatek,eye-vrt : u32, the selection of VRT reference voltage
Usually the digital and anolog phys use the same reference clock, but on some platforms, they are separated, so add another optional clock to support it. In order to keep the clock names consistent with PHY IP's, use the da_ref for anolog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)