From patchwork Sat Sep 17 21:40:14 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Blue Swirl X-Patchwork-Id: 115172 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 50A8CB7091 for ; Sun, 18 Sep 2011 07:40:52 +1000 (EST) Received: from localhost ([::1]:55034 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R52cw-00081I-BL for incoming@patchwork.ozlabs.org; Sat, 17 Sep 2011 17:40:46 -0400 Received: from eggs.gnu.org ([140.186.70.92]:54769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R52cq-00081D-Mp for qemu-devel@nongnu.org; Sat, 17 Sep 2011 17:40:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R52cp-0005TI-7N for qemu-devel@nongnu.org; Sat, 17 Sep 2011 17:40:40 -0400 Received: from mail-qy0-f180.google.com ([209.85.216.180]:52314) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R52co-0005T8-Vl for qemu-devel@nongnu.org; Sat, 17 Sep 2011 17:40:39 -0400 Received: by qyc1 with SMTP id 1so4879224qyc.4 for ; Sat, 17 Sep 2011 14:40:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=ebt/Zp0nuF/GVvbTzYl9y5Oeq+vLlK4JhrP+QqHrfeo=; b=iqvh0QXbzM/m1mWlOclSs1tC8HbHosryNhbjeCq3gqe97O8uWBsE9qZwoyHcQd+v82 6+t//A7Ldd6AgTbrgl1bigGFnWf03HkZppD/uMNioodj1OZt3L/NTWswUJKOIwFJio+e MNHJA9Ctstrr5qtKuznxELpOtX/6/DEPG7kxM= Received: by 10.224.210.137 with SMTP id gk9mr691371qab.209.1316295637950; Sat, 17 Sep 2011 14:40:37 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.6.129 with HTTP; Sat, 17 Sep 2011 14:40:14 -0700 (PDT) In-Reply-To: <4E71E219.9090306@redhat.com> References: <6BA6355D-D77A-40F4-A8C4-61901A926E71@suse.de> <4E6F1BAF.2000105@siemens.com> <2A74238E-5C89-444B-9DB9-4B380D182AC3@suse.de> <4E6F3FB8.6060705@siemens.com> <4E7053A3.8090508@redhat.com> <4E706303.9040502@redhat.com> <4E7063D9.3040803@siemens.com> <4E70645D.8050100@redhat.com> <4E7064BA.1050700@siemens.com> <58B7465A-925F-4732-A557-AB57BEFCD64B@suse.de> <4E706763.8020706@redhat.com> <14B02BB3-FFB5-4B67-B0AC-6E6A9806AE0E@suse.de> <219F7C53-89AB-4824-B78C-E31E99E3A50C@suse.de> <1316049883.455.178.camel@pasglop> <98A5FA69-192E-4CB6-846F-C296B825085C@suse.de> <1316080881.455.192.camel@pasglop> <4E71E219.9090306@redhat.com> From: Blue Swirl Date: Sat, 17 Sep 2011 21:40:14 +0000 Message-ID: To: Avi Kivity X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.216.180 Cc: Anthony Liguori , qemu-devel Developers , Alexander Graf , =?UTF-8?Q?Andreas_F=C3=A4rber?= , Gerd Hoffmann , Jan Kiszka , Richard Henderson Subject: Re: [Qemu-devel] [PATCH v3 5/6] vga: Use linear mapping + dirty logging in chain 4 memory access mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On Thu, Sep 15, 2011 at 11:31 AM, Avi Kivity wrote: > On 09/15/2011 01:01 PM, Benjamin Herrenschmidt wrote: >> >> >  Sure :). So the problem is that when emulating the G3 Beige machine in >> >  QEMU (default ppc32 target) we also add a PCI VGA adapter. Apparently, >> >  on x86 that PCI VGA adapter can map the special VGA regions to >> >  somewhere, namely 0xa0000. With the memory api overhaul, this also >> >  slipped into the PPC world where mapping 0xa0000 with VGA adapters is >> >  a pretty bad idea, as it's occupied by RAM. >> > >> >  Now the discussion was on which level that mapping would happen and >> >  which devices go through which buses which then would filter certain >> >  ranges from being mapped. Basically, which way does a memory request >> >  from the CPU go on a G3 Beige machine until it arrives the VGA >> >  adapter? >> > >> >  I hope that concludes the actual question. Avi, if I explained this >> >  wrong, please correct me. >> >> Ok so there's several things here. >> >> First, the mapping from CPU addresses to PCI addresses. This depends on >> the host bridge chip. The MPC106, used in the Beige G3, itself supports >> different type of mappings. >> >>  From memory, the way it's configured in a G3 is to have a 1:1 mapping of >> 80000000 CPU to 80000000 PCI. >> >> That means that with this basic mapping, you cannot generate memory >> accesses to low PCI addresses such as 0xa0000. > > Alex, what this means (I think is) that: pci_grackle_init() needs to create > a container memory region and pass it to pc_register_bus() as the pci > address space, and create and alias starting at 0x80000000 of the pci > address space, and map that alias at address 0x80000000 of the system > address space. > > See pc_init1() creating pci_memory and passing it to i440fx_init(), which > then maps some aliases into the system address space and also gives it to > pci_bus_new().  It's essentially the same thing with different details. I think the attached patch (on top of ppc-next) should do it, but it doesn't. Only the top area of the screen is shown, the rest is black. >> I don't remember (but it's possible) if it has another region which maps >> some other (high address) part of the address space down to 0 PCI. >> Typically that would be a smaller region which specifically allow access >> to the "ISA hole" that way. > > That would be done by mapping yet another alias. > > -- > error compiling committee.c: too many arguments to function > > From c07f1116220cba7d2ee769b03de59b5a874b76db Mon Sep 17 00:00:00 2001 Message-Id: From: Blue Swirl Date: Sat, 17 Sep 2011 20:30:50 +0000 Subject: [PATCH] PPC: use memory API to construct the PCI hole Avoid vga.chain4 mapping by constructing a PCI hole for upper 2G of the PCI space. Signed-off-by: Blue Swirl --- hw/grackle_pci.c | 11 ++++++++++- hw/ppc_newworld.c | 2 -- hw/ppc_oldworld.c | 2 -- hw/unin_pci.c | 18 ++++++++++++++++-- 4 files changed, 26 insertions(+), 7 deletions(-) diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c index 9d3ff7d..94a608e 100644 --- a/hw/grackle_pci.c +++ b/hw/grackle_pci.c @@ -41,6 +41,8 @@ typedef struct GrackleState { SysBusDevice busdev; PCIHostState host_state; + MemoryRegion pci_mmio; + MemoryRegion pci_hole; } GrackleState; /* Don't know if this matches real hardware, but it agrees with OHW. */ @@ -73,11 +75,18 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic, qdev_init_nofail(dev); s = sysbus_from_qdev(dev); d = FROM_SYSBUS(GrackleState, s); + + memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL); + memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio, + 0x80000000ULL, 0x7e000000ULL); + memory_region_add_subregion(address_space_mem, 0x80000000ULL, + &d->pci_hole); + d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", pci_grackle_set_irq, pci_grackle_map_irq, pic, - address_space_mem, + &d->pci_mmio, address_space_io, 0, 4); diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c index 5fb9359..bcdc0a3 100644 --- a/hw/ppc_newworld.c +++ b/hw/ppc_newworld.c @@ -263,8 +263,6 @@ static void ppc_core99_init (ram_addr_t ram_size, } } - isa_mem_base = 0x80000000; - /* Register 8 MB of ISA IO space */ isa_mmio_init(0xf2000000, 0x00800000); diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c index 3857075..5c17944 100644 --- a/hw/ppc_oldworld.c +++ b/hw/ppc_oldworld.c @@ -208,8 +208,6 @@ static void ppc_heathrow_init (ram_addr_t ram_size, } } - isa_mem_base = 0x80000000; - /* Register 2 MB of ISA IO space */ isa_mmio_init(0xfe000000, 0x00200000); diff --git a/hw/unin_pci.c b/hw/unin_pci.c index 600cd1e..4299052 100644 --- a/hw/unin_pci.c +++ b/hw/unin_pci.c @@ -41,6 +41,8 @@ static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e }; typedef struct UNINState { SysBusDevice busdev; PCIHostState host_state; + MemoryRegion pci_mmio; + MemoryRegion pci_hole; } UNINState; static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) @@ -215,10 +217,16 @@ PCIBus *pci_pmac_init(qemu_irq *pic, qdev_init_nofail(dev); s = sysbus_from_qdev(dev); d = FROM_SYSBUS(UNINState, s); + memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL); + memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio, + 0x80000000ULL, 0x70000000ULL); + memory_region_add_subregion(address_space_mem, 0x80000000ULL, + &d->pci_hole); + d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", pci_unin_set_irq, pci_unin_map_irq, pic, - address_space_mem, + &d->pci_mmio, address_space_io, PCI_DEVFN(11, 0), 4); @@ -272,10 +280,16 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic, s = sysbus_from_qdev(dev); d = FROM_SYSBUS(UNINState, s); + memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL); + memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio, + 0x80000000ULL, 0x70000000ULL); + memory_region_add_subregion(address_space_mem, 0x80000000ULL, + &d->pci_hole); + d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", pci_unin_set_irq, pci_unin_map_irq, pic, - address_space_mem, + &d->pci_mmio, address_space_io, PCI_DEVFN(11, 0), 4); -- 1.7.2.5