Patchwork [U-Boot,5/5] da8xx: print ARM and DDR frequency from u-boot

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Submitter nagabhushana.netagunte@ti.com
Date Sept. 17, 2011, 4:13 p.m.
Message ID <1316275984-11586-6-git-send-email-nagabhushana.netagunte@ti.com>
Download mbox | patch
Permalink /patch/115135/
State Superseded
Headers show

Comments

nagabhushana.netagunte@ti.com - Sept. 17, 2011, 4:13 p.m.
From: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>

print ARM and DDR frequency for da8xx as part of clocks
command and a function is added in hardware.h to find which
PLL clock is used.

Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/speed.c       |    7 +++++++
 arch/arm/include/asm/arch-davinci/hardware.h |   11 +++++++++++
 2 files changed, 18 insertions(+), 0 deletions(-)

Patch

diff --git a/arch/arm/cpu/arm926ejs/davinci/speed.c b/arch/arm/cpu/arm926ejs/davinci/speed.c
index 8650061..4bf72d5 100644
--- a/arch/arm/cpu/arm926ejs/davinci/speed.c
+++ b/arch/arm/cpu/arm926ejs/davinci/speed.c
@@ -194,6 +194,11 @@  int showclocks(cmd_tbl_t *cmdtp,
 	/* REVISIT fetch and display CPU ID and revision information
 	 * too ... that will matter as more revisions appear.
 	 */
+
+#ifdef CONFIG_SOC_DA8XX
+	printf("ARM Clock : %d Hz\n", clk_get(DAVINCI_ARM_CLKID));
+	printf("DDR Clock : %d Hz\n", clk_get(DAVINCI_DDR_CLKID)/2);
+#else
 	unsigned int pllbase;
 	unsigned int sysdiv;
 
@@ -225,6 +230,8 @@  int showclocks(cmd_tbl_t *cmdtp,
 	printf("\nDDR:   %d MHz\n",
 			/* DDR PHY uses an x2 input clock */
 			pll_sysclk_mhz(pllbase, sysdiv)/2);
+#endif
+
 	return 0;
 
 }
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 692d507..0ec594a 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -401,8 +401,13 @@  struct davinci_pllc_regs {
 #define DAVINCI_PLLC_DIV_MASK	0x1f
 
 #define ASYNC3          get_async3_src()
+#define EMIFB		get_emifb_src()
+
+#define PLL1_PLLM		((1 << 16) | DAVINCI_PLLM_CLKID)
+#define PLL1_SYSCLK1		((1 << 16) | 0x1)
 #define PLL1_SYSCLK2		((1 << 16) | 0x2)
 #define DAVINCI_SPI1_CLKID  (cpu_is_da830() ? 2 : ASYNC3)
+#define DAVINCI_DDR_CLKID	EMIFB
 /* Clock IDs */
 enum davinci_clk_ids {
 	DAVINCI_SPI0_CLKID = 2,
@@ -506,6 +511,12 @@  static inline int get_async3_src(void)
 			PLL1_SYSCLK2 : 2;
 }
 
+static inline int get_emifb_src(void)
+{
+	return (REG(&davinci_syscfg_regs->cfgchip3) & 0x80) ?
+			PLL1_PLLM : PLL1_SYSCLK1;
+}
+
 #endif /* CONFIG_SOC_DA8XX */
 
 #endif /* __ASM_ARCH_HARDWARE_H */