powerpc: Fix bogus cache flushing on all 40x and BookE processors

Submitted by Benjamin Herrenschmidt on Dec. 1, 2008, 6:01 a.m.

Details

Message ID 20081201060152.00DCCDDDE3@ozlabs.org
State Changes Requested, archived
Headers show

Commit Message

Benjamin Herrenschmidt Dec. 1, 2008, 6:01 a.m.
We were missing the CPU_FTR_NOEXECUTE bit in our cputable for all
these processors. The result is that update_mmu_cache() would flush
the cache for all pages mapped to userspace which is totally
unnecessary on those processors since we already handle flushing
on execute in the page fault path.

This should provide a nice speed up ;-)

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---

 arch/powerpc/include/asm/cputable.h |   13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

Comments

Kumar Gala Dec. 2, 2008, 7:36 a.m.
On Dec 1, 2008, at 12:01 AM, Benjamin Herrenschmidt wrote:

> We were missing the CPU_FTR_NOEXECUTE bit in our cputable for all
> these processors. The result is that update_mmu_cache() would flush
> the cache for all pages mapped to userspace which is totally
> unnecessary on those processors since we already handle flushing
> on execute in the page fault path.
>
> This should provide a nice speed up ;-)
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
>
> arch/powerpc/include/asm/cputable.h |   13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> --- linux-work.orig/arch/powerpc/include/asm/cputable.h	2008-12-01  
> 16:55:53.000000000 +1100
> +++ linux-work/arch/powerpc/include/asm/cputable.h	2008-12-01  
> 16:56:32.000000000 +1100
> @@ -366,19 +366,20 @@ extern const char *powerpc_base_platform
> #define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | \
> 	    CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
> #define CPU_FTRS_8XX	(CPU_FTR_USE_TB)
> -#define CPU_FTRS_40X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
> -#define CPU_FTRS_44X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
> +#define CPU_FTRS_40X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN |  
> CPU_FTR_NOEXECUTE)
> +#define CPU_FTRS_44X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN |  
> CPU_FTR_NOEXECUTE)
> #define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
> 	    CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
> -	    CPU_FTR_UNIFIED_ID_CACHE)
> +	    CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
> #define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
> -	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
> +	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP |  
> CPU_FTR_NODSISRALIGN \

Added a '|' at the end of the line before the escape

>
> +	    CPU_FTR_NOEXECUTE)
> #define CPU_FTRS_E500_2	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
> 	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
> -	    CPU_FTR_NODSISRALIGN)
> +	    CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
> #define CPU_FTRS_E500MC	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
> 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN  
> | \
> -	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
> +	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE)
> #define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)

- k
Benjamin Herrenschmidt Dec. 2, 2008, 9:20 a.m.
On Tue, 2008-12-02 at 01:36 -0600, Kumar Gala wrote:

> > #define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
> > 	    CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
> > -	    CPU_FTR_UNIFIED_ID_CACHE)
> > +	    CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
> > #define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
> > -	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
> > +	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP |  
> > CPU_FTR_NODSISRALIGN \
> 
> Added a '|' at the end of the line before the escape

Right. Will send a new patch tomorrow. Appart from that, have you
verified it doesn't have any adverse effects for you ? I did some quick
tests on 440 and things seem to be fine.

Cheers,
Ben.
Steven A. Falco Dec. 2, 2008, 3:41 p.m.
Kumar Gala wrote:
> 
> 
> On Dec 1, 2008, at 12:01 AM, Benjamin Herrenschmidt wrote:
> 
>> We were missing the CPU_FTR_NOEXECUTE bit in our cputable for all
>> these processors. The result is that update_mmu_cache() would flush
>> the cache for all pages mapped to userspace which is totally
>> unnecessary on those processors since we already handle flushing
>> on execute in the page fault path.
>>
>> This should provide a nice speed up ;-)
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

I'm running with your patch on a 440 Sequoia board, and it
works fine for me.

Acked-by: Steven A. Falco <sfalco@harris.com>

	Steve
Trent Piepho Dec. 3, 2008, 11:09 p.m.
On Tue, 2 Dec 2008, Benjamin Herrenschmidt wrote:
> On Tue, 2008-12-02 at 01:36 -0600, Kumar Gala wrote:
>
>>> #define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
>>> 	    CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
>>> -	    CPU_FTR_UNIFIED_ID_CACHE)
>>> +	    CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
>>> #define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
>>> -	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
>>> +	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP |
>>> CPU_FTR_NODSISRALIGN \
>>
>> Added a '|' at the end of the line before the escape
>
> Right. Will send a new patch tomorrow. Appart from that, have you
> verified it doesn't have any adverse effects for you ? I did some quick
> tests on 440 and things seem to be fine.


#ifdef __powerpc64__
#define LONG_ASM_CONST(x)               ASM_CONST(x)
#else
#define LONG_ASM_CONST(x)               0
#endif

#define CPU_FTR_NOEXECUTE               LONG_ASM_CONST(0x0000000800000000)

Am I not looking at the right code?  Since e200 and e500 aren't powerpc64,
doesn't adding CPU_FTR_NOEXECUTE have no effect at all?
Benjamin Herrenschmidt Dec. 4, 2008, 12:06 a.m.
On Wed, 2008-12-03 at 15:09 -0800, Trent Piepho wrote:

> #ifdef __powerpc64__
> #define LONG_ASM_CONST(x)               ASM_CONST(x)
> #else
> #define LONG_ASM_CONST(x)               0
> #endif
> 
> #define CPU_FTR_NOEXECUTE               LONG_ASM_CONST(0x0000000800000000)
> 
> Am I not looking at the right code?  Since e200 and e500 aren't powerpc64,
> doesn't adding CPU_FTR_NOEXECUTE have no effect at all?

No, you are right, this is a case where I didn't actually verify that
the patch had the expected effect :-(

We are running out of low FTR bits, heck, I might make them 64-bit
for everybody soon.

I'll fix that up, thanks for spotting it.

Cheers,
Ben.

Patch hide | download patch | download mbox

--- linux-work.orig/arch/powerpc/include/asm/cputable.h	2008-12-01 16:55:53.000000000 +1100
+++ linux-work/arch/powerpc/include/asm/cputable.h	2008-12-01 16:56:32.000000000 +1100
@@ -366,19 +366,20 @@  extern const char *powerpc_base_platform
 #define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | \
 	    CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
 #define CPU_FTRS_8XX	(CPU_FTR_USE_TB)
-#define CPU_FTRS_40X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_44X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
+#define CPU_FTRS_40X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
+#define CPU_FTRS_44X	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
 	    CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
-	    CPU_FTR_UNIFIED_ID_CACHE)
+	    CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
-	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
+	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN \
+	    CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_E500_2	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
-	    CPU_FTR_NODSISRALIGN)
+	    CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_E500MC	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
-	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
+	    CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE)
 #define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 
 /* 64-bit CPUs */