| Message ID | 20190821055530.8720-4-joel@jms.id.au |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | ARM: Add ASPEED AST2600 support | expand |
On Wed, 21 Aug 2019, at 15:26, Joel Stanley wrote: > The AST2600 is a Cortex A7 dual core CPU that uses the ARM GIC for > interrupts and ARM timer as a clocksource. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > --- > arch/arm/mach-aspeed/Kconfig | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig > index 2979aa4daeea..56007b0b6120 100644 > --- a/arch/arm/mach-aspeed/Kconfig > +++ b/arch/arm/mach-aspeed/Kconfig > @@ -1,7 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0-only > menuconfig ARCH_ASPEED > bool "Aspeed BMC architectures" > - depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 > + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7 > select SRAM > select WATCHDOG > select ASPEED_WATCHDOG > @@ -33,4 +33,16 @@ config MACH_ASPEED_G5 > Say yes if you intend to run on an Aspeed ast2500 or similar > fifth generation Aspeed BMCs. > > +config MACH_ASPEED_G6 > + bool "Aspeed SoC 6th Generation" > + depends on ARCH_MULTI_V7 > + select CPU_V7 > + select PINCTRL_ASPEED_G6 > + select ARM_GIC > + select HAVE_ARM_ARCH_TIMER > + select HAVE_SMP > + help > + Say yes if you intend to run on an Aspeed ast2600 or similar > + sixth generation Aspeed BMCs. > + > endif > -- > 2.23.0.rc1 > >
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index 2979aa4daeea..56007b0b6120 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only menuconfig ARCH_ASPEED bool "Aspeed BMC architectures" - depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7 select SRAM select WATCHDOG select ASPEED_WATCHDOG @@ -33,4 +33,16 @@ config MACH_ASPEED_G5 Say yes if you intend to run on an Aspeed ast2500 or similar fifth generation Aspeed BMCs. +config MACH_ASPEED_G6 + bool "Aspeed SoC 6th Generation" + depends on ARCH_MULTI_V7 + select CPU_V7 + select PINCTRL_ASPEED_G6 + select ARM_GIC + select HAVE_ARM_ARCH_TIMER + select HAVE_SMP + help + Say yes if you intend to run on an Aspeed ast2600 or similar + sixth generation Aspeed BMCs. + endif
The AST2600 is a Cortex A7 dual core CPU that uses the ARM GIC for interrupts and ARM timer as a clocksource. Signed-off-by: Joel Stanley <joel@jms.id.au> --- arch/arm/mach-aspeed/Kconfig | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-)