| Message ID | 1316187462-21074-1-git-send-email-galak@kernel.crashing.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Kumar Gala |
| Headers | show |
On 09/16/2011 10:37 AM, Kumar Gala wrote: > From: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> > > e500mc and e5500 share some eary setup code that need r5 to point to the > cpu spec structure. setup_cpu_e500mc() sets it but setup_cpu_e5500() > didn't. > > This caused a crash on 32 bit e5500 running under hypervisor, when > __setup_e500mc_ivors() tried to access the cpu features field. > > Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > --- > arch/powerpc/kernel/cpu_setup_fsl_booke.S | 3 ++- > 1 files changed, 2 insertions(+), 1 deletions(-) Unless I missed something going in recently, there's nothing in the mainline kernel that uses r5 in __setup_e500mc_ivors(). This is a fix for code that is currently just in our SDK, and should be combined with that code when it is posted. The interprocedural register allocation could stand to be done more simply as well (why not just pick a different register for lr, and leave r4 where it is?), and should be documented. -Scott
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 8053db0..f9f6a6f 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -1,7 +1,7 @@ /* * This file contains low level CPU setup functions. * Kumar Gala <galak@kernel.crashing.org> - * Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2009,2011 Freescale Semiconductor, Inc. * * Based on cpu_setup_6xx code by * Benjamin Herrenschmidt <benh@kernel.crashing.org> @@ -83,6 +83,7 @@ _GLOBAL(__setup_cpu_e500mc) /* Right now, restore and setup are the same thing */ _GLOBAL(__restore_cpu_e5500) _GLOBAL(__setup_cpu_e5500) + mr r5, r4 mflr r4 bl __e500_icache_setup bl __e500_dcache_setup