| Message ID | 1566191521-7820-28-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: sifive_u: Improve the emulation fidelity of sifive_u machine | expand |
On Sun, Aug 18, 2019 at 10:31 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > In the past we did not have a model for PRCI, hence two handcrafted > clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the > purpose of supplying hard-coded clock frequencies. But now since we > have added the PRCI support in QEMU, we don't need them any more. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > > --- > > Changes in v4: > - new patch to remove handcrafted clock nodes for UART and ethernet > > Changes in v3: None > Changes in v2: None > > hw/riscv/sifive_u.c | 24 +----------------------- > include/hw/riscv/sifive_u.h | 3 +-- > 2 files changed, 2 insertions(+), 25 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 7a370e9..7d9fb3a 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -89,8 +89,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > uint32_t *cells; > char *nodename; > char ethclk_names[] = "pclk\0hclk"; > - uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; > - uint32_t uartclk_phandle; > + uint32_t plic_phandle, prci_phandle, phandle = 1; > uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; > > fdt = s->fdt = create_device_tree(&s->fdt_size); > @@ -250,17 +249,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > g_free(cells); > g_free(nodename); > > - ethclk_phandle = phandle++; > - nodename = g_strdup_printf("/soc/ethclk"); > - qemu_fdt_add_subnode(fdt, nodename); > - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); > - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); > - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", > - SIFIVE_U_GEM_CLOCK_FREQ); > - qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); > - ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); > - g_free(nodename); > - > phy_phandle = phandle++; > nodename = g_strdup_printf("/soc/ethernet@%lx", > (long)memmap[SIFIVE_U_GEM].base); > @@ -292,16 +280,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); > g_free(nodename); > > - uartclk_phandle = phandle++; > - nodename = g_strdup_printf("/soc/uartclk"); > - qemu_fdt_add_subnode(fdt, nodename); > - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); > - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); > - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); > - qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle); > - uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename); > - g_free(nodename); > - > nodename = g_strdup_printf("/soc/serial@%lx", > (long)memmap[SIFIVE_U_UART0].base); > qemu_fdt_add_subnode(fdt, nodename); > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index cba29e1..8880f9c 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -72,8 +72,7 @@ enum { > enum { > SIFIVE_U_CLOCK_FREQ = 1000000000, > SIFIVE_U_HFCLK_FREQ = 33333333, > - SIFIVE_U_RTCCLK_FREQ = 1000000, > - SIFIVE_U_GEM_CLOCK_FREQ = 125000000 > + SIFIVE_U_RTCCLK_FREQ = 1000000 > }; > > #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 > -- > 2.7.4 > >
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7a370e9..7d9fb3a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -89,8 +89,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, uint32_t *cells; char *nodename; char ethclk_names[] = "pclk\0hclk"; - uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; - uint32_t uartclk_phandle; + uint32_t plic_phandle, prci_phandle, phandle = 1; uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); @@ -250,17 +249,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(cells); g_free(nodename); - ethclk_phandle = phandle++; - nodename = g_strdup_printf("/soc/ethclk"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_GEM_CLOCK_FREQ); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); - ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - phy_phandle = phandle++; nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); @@ -292,16 +280,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); - uartclk_phandle = phandle++; - nodename = g_strdup_printf("/soc/uartclk"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle); - uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - nodename = g_strdup_printf("/soc/serial@%lx", (long)memmap[SIFIVE_U_UART0].base); qemu_fdt_add_subnode(fdt, nodename); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index cba29e1..8880f9c 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -72,8 +72,7 @@ enum { enum { SIFIVE_U_CLOCK_FREQ = 1000000000, SIFIVE_U_HFCLK_FREQ = 33333333, - SIFIVE_U_RTCCLK_FREQ = 1000000, - SIFIVE_U_GEM_CLOCK_FREQ = 125000000 + SIFIVE_U_RTCCLK_FREQ = 1000000 }; #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
In the past we did not have a model for PRCI, hence two handcrafted clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the purpose of supplying hard-coded clock frequencies. But now since we have added the PRCI support in QEMU, we don't need them any more. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- Changes in v4: - new patch to remove handcrafted clock nodes for UART and ethernet Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 24 +----------------------- include/hw/riscv/sifive_u.h | 3 +-- 2 files changed, 2 insertions(+), 25 deletions(-)