From patchwork Fri Aug 16 19:41:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1148401 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="WixfZAc9"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 469DHH73wfz9sBF for ; Sat, 17 Aug 2019 05:42:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727593AbfHPTmS (ORCPT ); Fri, 16 Aug 2019 15:42:18 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:13152 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727557AbfHPTmS (ORCPT ); Fri, 16 Aug 2019 15:42:18 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 16 Aug 2019 12:42:20 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 16 Aug 2019 12:42:17 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 16 Aug 2019 12:42:17 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 16 Aug 2019 19:42:17 +0000 Received: from HQMAIL111.nvidia.com (172.20.187.18) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 16 Aug 2019 19:42:17 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 16 Aug 2019 19:42:17 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.166.126]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 16 Aug 2019 12:42:17 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 02/22] pinctrl: tegra: Flush pinctrl writes during resume Date: Fri, 16 Aug 2019 12:41:47 -0700 Message-ID: <1565984527-5272-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565984527-5272-1-git-send-email-skomatineni@nvidia.com> References: <1565984527-5272-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1565984541; bh=VHDrtC8ZGPiMwrhvcDYGr1zYEWJZ5BoN1NN2rqR7JiI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=WixfZAc9ExfMuDT1FqsRjpvMy9ssde3X9yxS3uG4+KykQtCXbKSxO59f1LHwtsUU9 wa4qmlc4f9e2lXfQOkJ01TMwwe0kcBlycHstV374nDSqiLoy90BMzhsmGnDLMm9513 Wf/Kfcu5bhAh4kdrKeUgi/hbddwYBFceZ5Nc+hf9Usa3QYOSU2vOTuSdScrk62gSvl f1ZntADlZGmnNoTU/k/BCrRr9/+wNYWqX0gwNzTXiHv4uvgbljF/uRGU/dswHCOSTa qgwfHCSj0+BKz20KIKg9Njpw1azzVMrQJ+vu8VtVtzLRhUEL+yaTI0QR4Y2NW8WqoQ 3Cn0B4AzVjxRw== Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch adds pinctrl register read to flush all the prior pinctrl writes and then adds barrier for pinctrl register read to complete during resume to make sure all pinctrl changes are effective. Acked-by: Thierry Reding Reviewed-by: Dmitry Osipenko Signed-off-by: Sowjanya Komatineni --- drivers/pinctrl/tegra/pinctrl-tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 5e3c00137d71..e9a7cbb9aa33 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -677,6 +677,10 @@ static int tegra_pinctrl_resume(struct device *dev) writel_relaxed(*backup_regs++, regs++); } + /* flush all the prior writes */ + readl_relaxed(pmx->regs[0]); + /* wait for pinctrl register read to complete */ + rmb(); return 0; }