@@ -55,6 +55,7 @@ typedef struct MCHPCIState {
MemoryRegion smram_region, open_high_smram;
MemoryRegion smram, low_smram, high_smram;
MemoryRegion tseg_blackhole, tseg_window;
+ MemoryRegion smbase, smram_alias;
Range pci_hole;
uint64_t below_4g_mem_size;
uint64_t above_4g_mem_size;
@@ -574,6 +574,16 @@ static void mch_realize(PCIDevice *d, Error **errp)
memory_region_set_enabled(&mch->tseg_window, false);
memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size,
&mch->tseg_window);
+
+ memory_region_init_ram(&mch->smm_base, OBJECT(mch), "SMM BASE", MCH_HOST_BRIDGE_SMRAM_C_SIZE, &error_fatal);
+ memory_region_set_enabled(&mch->smm_base, true);
+ memory_region_add_subregion(&mch->smram, 0x30000, &mch->smm_base);
+
+ memory_region_init_alias(&mch->smm_base_alias, OBJECT(mch), "smim_base_alias",
+ &mch->smm_base, 0, MCH_HOST_BRIDGE_SMRAM_C_SIZE);
+ memory_region_set_enabled(&mch->smm_base_alias, true);
+ memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, &mch->smm_base_alias, 1);
+
object_property_add_const_link(qdev_get_machine(), "smram",
OBJECT(&mch->smram), &error_abort);
it will allow us to hide sensetive SMM_BASE area from non SMM running env, that will allow us to ensure that hotplugged CPU will run trusted SMM BASE relocation code and we won't need to force all present CPUs into SMM mode since we don not care about about 0x30000 content in normal RAM address space. it's a obviously a hack only to demo approach. for easy SMI initialization on SMI entry point SMRAM is aliased in to hajaked normal RAM address space at a0000. Patch should be used with supplied SMBIOS patch, that drops save/restore sequence and just inits SMI entry point. to test to run: qemu-system-x86_64 -M q35 -bios /path_to_seabios/out/bios.bin \ -nodefaults \ -chardev stdio,id=seabios -device isa-debugcon,iobase=0x402,chardev=seabios Signed-off-by: Igor Mammedov <imammedo@redhat.com> --- include/hw/pci-host/q35.h | 1 + hw/pci-host/q35.c | 10 ++++++++++ 2 files changed, 11 insertions(+)