| Message ID | 20190815083716.4715-8-xiaowei.bao@nxp.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [01/10] PCI: designware-ep: Add multiple PFs support for DWC | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch next (da206bd46848568e1aaf35f00e2d78bf9bc94f95) |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 7 lines checked |
On Thu, 15 Aug 2019 16:37:14 +0800, Xiaowei Bao wrote: > Add the pf-offset property for multiple PF. > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> > --- > Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 5561a1c..d658687 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -43,6 +43,7 @@ RC mode: EP mode: - max-functions: maximum number of functions that can be configured +- pf-offset: the offset of each PF's config space Example configuration:
Add the pf-offset property for multiple PF. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> --- Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 + 1 file changed, 1 insertion(+)