From patchwork Thu Aug 15 08:55:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1147499 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-507026-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="LT5k0h4X"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 468L070rYtz9sN6 for ; Thu, 15 Aug 2019 18:56:06 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=BxCufxEAe4E4WPEmDeHIyVjsPfMosW/n3Oh175ycMhJ8ZQ1290FJQ CY29EpUNW6MI0KG7UHGgBEXeC6dsSdrHVLNGZB9cuLc4qXPC9Zgy9F2HJ4b9wrVh L3P84NQKz1EwRenKvvN0XYLWodke2WNX+RmEWirD3ZKjhOAKaBfw9w= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=p/yiZ3iiZSHNt7Z3IUfc6YvxHMg=; b=LT5k0h4XgYgz9e43kDbn XxfG8WAbfsH6E56Ch1LXxdbfaybsLiVFcLVimtYkwhMJJow1BFKBDn9m8d6rV2JZ ode87QaOvq71kYN0Te+skGenzOjYN0B1+Ol/j23PwINRhwK+RMqqgWGlrGHedcW8 qCttM/TJxl/SZq6ezxO7wBs= Received: (qmail 9860 invoked by alias); 15 Aug 2019 08:55:59 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 9055 invoked by uid 89); 15 Aug 2019 08:55:59 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS autolearn=ham version=3.3.1 spammy=pcb, Upa, upa, our X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Aug 2019 08:55:58 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8C43F28 for ; Thu, 15 Aug 2019 01:55:56 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 334303F706 for ; Thu, 15 Aug 2019 01:55:56 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed][AArch64] Tweak operand choice for SVE predicate AND Date: Thu, 15 Aug 2019 09:55:55 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes SVE defines an assembly alias: MOV pa.B, pb/Z, pc.B -> AND pa.B. pb/Z, pc.B, pc.B Our and3 pattern was instead using the functionally-equivalent: AND pa.B. pb/Z, pb.B, pc.B ^^^^ This patch duplicates pc.B instead so that the alias can be seen in disassembly. I wondered about using the alias in the pattern instead, but using AND explicitly seems to fit better with the pattern name and surrounding code. Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. Applied as r274521. Richard 2019-08-15 Richard Sandiford gcc/ * config/aarch64/aarch64-sve.md (and3): Make the operand order match the MOV /Z alias. Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-08-15 09:47:20.176358327 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-08-15 09:54:12.977312970 +0100 @@ -3317,12 +3317,14 @@ (define_insn "*3" ;; ------------------------------------------------------------------------- ;; Predicate AND. We can reuse one of the inputs as the GP. +;; Doubling the second operand is the preferred implementation +;; of the MOV alias, so we use that instead of %1/z, %1, %2. (define_insn "and3" [(set (match_operand:PRED_ALL 0 "register_operand" "=Upa") (and:PRED_ALL (match_operand:PRED_ALL 1 "register_operand" "Upa") (match_operand:PRED_ALL 2 "register_operand" "Upa")))] "TARGET_SVE" - "and\t%0.b, %1/z, %1.b, %2.b" + "and\t%0.b, %1/z, %2.b, %2.b" ) ;; Unpredicated predicate EOR and ORR.