[OpenWrt-Devel,2/3] kernel: rtl8367b: add configuration for extended interface 2
diff mbox series

Message ID 62bc7812-4435-54d7-f5f4-30f5bed6d249@yandex.ru
State Changes Requested, archived
Headers show
Series
  • kernel: add support for realtek rtl8367s
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Commit Message

Serge Vailugin Aug. 15, 2019, 8:28 a.m. UTC
Both rtl8367b and rtl8367s have two extended interface
rtl8367rb: 5 port + 2*RGMII/MII
rtl8367s:  5 port + SGMII/HSGMI + RGMII/MII
(?)rtl8367sb:  5 port + 2*RGMII/MII
These interfaces correpond to EXT1 and EXT2 (ports 6 and 7 respectivly).
Current driver don't support EXT2 configuration but notexisting EXT0 
(port 5).
This patch allow to configure EXT2 in dts-file:

	rtl8367rb {
		compatible = "realtek,rtl8367b";
		cpu_port = <7>;
		realtek,extif2 = <1 0 1 1 1 1 1 1 2>; /* configuration for EXT2 */
		mii-bus = <&mdio0>;
		phy_id = <29>;
	};

This patch is independent of the rtl8366_smi patch (set switch phy address)
and may be helpful for device with rtl8367rb connected through EXT2.

Signed-off-by: Serge Vasilugin <vasilugin@yandex.ru>


---
serge

Comments

Vincent Wiemann Aug. 17, 2019, 6:02 p.m. UTC | #1
On 15.08.19 10:28, Serge Vasilugin wrote:
> Both rtl8367b and rtl8367s have two extended interface
> rtl8367rb: 5 port + 2*RGMII/MII
> rtl8367s:  5 port + SGMII/HSGMI + RGMII/MII
> (?)rtl8367sb:  5 port + 2*RGMII/MII
> These interfaces correpond to EXT1 and EXT2 (ports 6 and 7 respectivly).
> Current driver don't support EXT2 configuration but notexisting EXT0 (port 5).
> This patch allow to configure EXT2 in dts-file:
> 
>     rtl8367rb {
>         compatible = "realtek,rtl8367b";
>         cpu_port = <7>;
>         realtek,extif2 = <1 0 1 1 1 1 1 1 2>; /* configuration for EXT2 */
>         mii-bus = <&mdio0>;
>         phy_id = <29>;
>     };
> 
> This patch is independent of the rtl8366_smi patch (set switch phy address)
> and may be helpful for device with rtl8367rb connected through EXT2.
> 
> Signed-off-by: Serge Vasilugin <vasilugin@yandex.ru>
> 
> --- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c
> +++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c
> @@ -137,19 +137,30 @@
> 
>  #define RTL8367B_CHIP_DEBUG1_REG        0x1304
> 
> +/* extif2 setup register */
> +#define RTL8367B_CHIP_DEBUG2_REG        0x13e2
> +
>  #define RTL8367B_DIS_REG            0x1305
>  #define   RTL8367B_DIS_SKIP_MII_RXER(_x)    BIT(12 + (_x))

One space too much after "define". Please use TABs for indentation before values.

>  #define   RTL8367B_DIS_RGMII_SHIFT(_x)        (4 * (_x))
>  #define   RTL8367B_DIS_RGMII_MASK        0x7
> 
> -#define RTL8367B_EXT_RGMXF_REG(_x)        (0x1306 + (_x))
> +/* extif2 digital interface select */
> +#define RTL8367B_DIS2_REG            0x13c3
> +#define    RTL8367B_DIS2_SKIP_MII_RXER_SHIFT    4
> +#define    RTL8367B_DIS2_SKIP_MII_RXER    0x10
> +#define    RTL8367B_DIS2_RGMII_SHIFT    0
> +#define    RTL8367B_DIS2_RGMII_MASK    0xF
> +/* extif2 delay config register == 0x13c5 */
> +#define RTL8367B_EXT_RGMXF_REG(_x)        ((_x) == 2 ? 0x13c5 : 0x1306 + (_x))
>  #define   RTL8367B_EXT_RGMXF_DUMMY0_SHIFT    5
>  #define   RTL8367B_EXT_RGMXF_DUMMY0_MASK    0x7ff
>  #define   RTL8367B_EXT_RGMXF_TXDELAY_SHIFT    3
>  #define   RTL8367B_EXT_RGMXF_TXDELAY_MASK    1
>  #define   RTL8367B_EXT_RGMXF_RXDELAY_MASK    0x7
> 
> -#define RTL8367B_DI_FORCE_REG(_x)        (0x1310 + (_x))
> +/* extif2 digital interface force register == 0x13c4 */
> +#define RTL8367B_DI_FORCE_REG(_x)        ((_x) == 2 ? 0x13c4 : 0x1310 + (_x))
>  #define   RTL8367B_DI_FORCE_MODE        BIT(12)
>  #define   RTL8367B_DI_FORCE_NWAY        BIT(7)
>  #define   RTL8367B_DI_FORCE_TXPAUSE        BIT(6)
> @@ -754,8 +844,9 @@ static int rtl8367b_extif_set_mode(struc
>      switch (mode) {
>      case RTL8367_EXTIF_MODE_RGMII:
>      case RTL8367_EXTIF_MODE_RGMII_33V:
> -        REG_WR(smi, RTL8367B_CHIP_DEBUG0_REG, 0x0367);
> +        REG_WR(smi, RTL8367B_CHIP_DEBUG0_REG, 0x0767);
>          REG_WR(smi, RTL8367B_CHIP_DEBUG1_REG, 0x7777);
> +        REG_WR(smi, RTL8367B_CHIP_DEBUG2_REG, 0x01fd);
>          break;
> 
>      case RTL8367_EXTIF_MODE_TMII_MAC:
> @@ -785,9 +876,14 @@ static int rtl8367b_extif_set_mode(struc
>          return -EINVAL;
>      }
> 
> -    REG_RMW(smi, RTL8367B_DIS_REG,
> -        RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
> -        mode << RTL8367B_DIS_RGMII_SHIFT(id));
> +    if(id < 2)
> +        REG_RMW(smi, RTL8367B_DIS_REG,
> +            RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
> +            mode << RTL8367B_DIS_RGMII_SHIFT(id));
> +    else
> +        REG_RMW(smi, RTL8367B_DIS2_REG,
> +            RTL8367B_DIS2_RGMII_MASK << RTL8367B_DIS2_RGMII_SHIFT,
> +            mode << RTL8367B_DIS2_RGMII_SHIFT);
> 
>      return 0;
>  }
> @@ -931,6 +1027,10 @@ static int rtl8367b_setup(struct rtl8366
>          err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1");
>          if (err)
>              return err;
> +
> +        err = rtl8367b_extif_init_of(smi, 2, "realtek,extif2");
> +        if (err)
> +            return err;
>      } else {
>          err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);
>          if (err)
> 
> ---
> serge
> 
> _______________________________________________
> openwrt-devel mailing list
> openwrt-devel@lists.openwrt.org
> https://lists.openwrt.org/mailman/listinfo/openwrt-devel
>

Patch
diff mbox series

--- a/target/linux/generic/files/drivers/net/phy/rtl8367b.c
+++ b/target/linux/generic/files/drivers/net/phy/rtl8367b.c
@@ -137,19 +137,30 @@ 

  #define RTL8367B_CHIP_DEBUG1_REG		0x1304

+/* extif2 setup register */
+#define RTL8367B_CHIP_DEBUG2_REG		0x13e2
+
  #define RTL8367B_DIS_REG			0x1305
  #define   RTL8367B_DIS_SKIP_MII_RXER(_x)	BIT(12 + (_x))
  #define   RTL8367B_DIS_RGMII_SHIFT(_x)		(4 * (_x))
  #define   RTL8367B_DIS_RGMII_MASK		0x7

-#define RTL8367B_EXT_RGMXF_REG(_x)		(0x1306 + (_x))
+/* extif2 digital interface select */
+#define RTL8367B_DIS2_REG			0x13c3
+#define    RTL8367B_DIS2_SKIP_MII_RXER_SHIFT    4
+#define    RTL8367B_DIS2_SKIP_MII_RXER    0x10
+#define    RTL8367B_DIS2_RGMII_SHIFT    0
+#define    RTL8367B_DIS2_RGMII_MASK    0xF
+/* extif2 delay config register == 0x13c5 */
+#define RTL8367B_EXT_RGMXF_REG(_x)		((_x) == 2 ? 0x13c5 : 0x1306 + (_x))
  #define   RTL8367B_EXT_RGMXF_DUMMY0_SHIFT	5
  #define   RTL8367B_EXT_RGMXF_DUMMY0_MASK	0x7ff
  #define   RTL8367B_EXT_RGMXF_TXDELAY_SHIFT	3
  #define   RTL8367B_EXT_RGMXF_TXDELAY_MASK	1
  #define   RTL8367B_EXT_RGMXF_RXDELAY_MASK	0x7

-#define RTL8367B_DI_FORCE_REG(_x)		(0x1310 + (_x))
+/* extif2 digital interface force register == 0x13c4 */
+#define RTL8367B_DI_FORCE_REG(_x)		((_x) == 2 ? 0x13c4 : 0x1310 + (_x))
  #define   RTL8367B_DI_FORCE_MODE		BIT(12)
  #define   RTL8367B_DI_FORCE_NWAY		BIT(7)
  #define   RTL8367B_DI_FORCE_TXPAUSE		BIT(6)
@@ -754,8 +844,9 @@  static int rtl8367b_extif_set_mode(struc
  	switch (mode) {
  	case RTL8367_EXTIF_MODE_RGMII:
  	case RTL8367_EXTIF_MODE_RGMII_33V:
-		REG_WR(smi, RTL8367B_CHIP_DEBUG0_REG, 0x0367);
+		REG_WR(smi, RTL8367B_CHIP_DEBUG0_REG, 0x0767);
  		REG_WR(smi, RTL8367B_CHIP_DEBUG1_REG, 0x7777);
+		REG_WR(smi, RTL8367B_CHIP_DEBUG2_REG, 0x01fd);
  		break;

  	case RTL8367_EXTIF_MODE_TMII_MAC:
@@ -785,9 +876,14 @@  static int rtl8367b_extif_set_mode(struc
  		return -EINVAL;
  	}

-	REG_RMW(smi, RTL8367B_DIS_REG,
-		RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
-		mode << RTL8367B_DIS_RGMII_SHIFT(id));
+	if(id < 2)
+		REG_RMW(smi, RTL8367B_DIS_REG,
+			RTL8367B_DIS_RGMII_MASK << RTL8367B_DIS_RGMII_SHIFT(id),
+			mode << RTL8367B_DIS_RGMII_SHIFT(id));
+	else
+		REG_RMW(smi, RTL8367B_DIS2_REG,
+			RTL8367B_DIS2_RGMII_MASK << RTL8367B_DIS2_RGMII_SHIFT,
+			mode << RTL8367B_DIS2_RGMII_SHIFT);

  	return 0;
  }
@@ -931,6 +1027,10 @@  static int rtl8367b_setup(struct rtl8366
  		err = rtl8367b_extif_init_of(smi, 1, "realtek,extif1");
  		if (err)
  			return err;
+
+		err = rtl8367b_extif_init_of(smi, 2, "realtek,extif2");
+		if (err)
+			return err;
  	} else {
  		err = rtl8367b_extif_init(smi, 0, pdata->extif0_cfg);
  		if (err)