| Message ID | 1316045346-5168-2-git-send-email-marek.vasut@gmail.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Stefano Babic |
| Headers | show |
On Thu, Sep 15, 2011 at 8:09 AM, Marek Vasut <marek.vasut@gmail.com> wrote: > The PLL decoding algorithm didn't take into account many configuration bits. > Adjust it according to Linux kernel. Also, add PLL4 for MX53. > > Signed-off-by: Marek Vasut <marek.vasut@gmail.com> > --- > arch/arm/cpu/armv7/mx5/clock.c | 77 ++++++++++++++++++++++++++---- > arch/arm/include/asm/arch-mx5/imx-regs.h | 3 + > 2 files changed, 70 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c > index 00610a0..9f37f7f 100644 > --- a/arch/arm/cpu/armv7/mx5/clock.c > +++ b/arch/arm/cpu/armv7/mx5/clock.c > @@ -29,11 +29,13 @@ > #include <asm/arch/imx-regs.h> > #include <asm/arch/crm_regs.h> > #include <asm/arch/clock.h> > +#include <div64.h> > > enum pll_clocks { > PLL1_CLOCK = 0, > PLL2_CLOCK, > PLL3_CLOCK, > + PLL4_CLOCK, > PLL_CLOCKS, > }; > > @@ -41,25 +43,76 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { > [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR, > [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR, > [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR, > +#ifdef CONFIG_MX53 > + [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR, > +#endif > }; > > +#define MXC_DPLLC_CTL_HFSM (1 << 7) > +#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) > + > +#define MXC_DPLLC_OP_PDF_MASK 0xf > +#define MXC_DPLLC_OP_MFI_MASK (0xf << 4) > +#define MXC_DPLLC_OP_MFI_OFFSET 4 > + > +#define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff > + > +#define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff Can we put this stuff to crm_reg.h file? > + > struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; > > /* > - * Calculate the frequency of this pll. > + * Calculate the frequency of PLLn. > */ > -static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq) > +static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) I found that you prefer to using the uint32_t than u32? what's the rule for u-boot? Wolfgang? > { > - u32 mfi, mfn, mfd, pd; > + uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret; > + uint64_t refclk, temp; > + int32_t mfn_abs; > + > + ctrl = readl(&pll->ctrl); > + > + if (ctrl & MXC_DPLLC_CTL_HFSM) { > + mfn = __raw_readl(&pll->hfs_mfn); > + mfd = __raw_readl(&pll->hfs_mfd); > + op = __raw_readl(&pll->hfs_op); > + } else { > + mfn = __raw_readl(&pll->mfn); > + mfd = __raw_readl(&pll->mfd); > + op = __raw_readl(&pll->op); > + } > > - mfn = __raw_readl(&pll->mfn); > - mfd = __raw_readl(&pll->mfd) + 1; > - mfi = __raw_readl(&pll->op); > - pd = (mfi & 0xF) + 1; > - mfi = (mfi >> 4) & 0xF; > - mfi = (mfi >= 5) ? mfi : 5; > + mfd &= MXC_DPLLC_MFD_MFD_MASK; > + mfn &= MXC_DPLLC_MFN_MFN_MASK; > + pdf = op & MXC_DPLLC_OP_PDF_MASK; > + mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET; > + > + /* 21.2.3 */ > + if (mfi < 5) > + mfi = 5; > + > + /* Sign extend */ > + if (mfn >= 0x04000000) { > + mfn |= 0xfc000000; > + mfn_abs = -mfn; > + } else > + mfn_abs = mfn; > + > + refclk = infreq * 2; > + if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN) > + refclk *= 2; > + > + refclk /= pdf + 1; > + temp = refclk * mfn_abs; > + do_div(temp, mfd + 1); > + ret = refclk * mfi; > + > + if ((int)mfn < 0) > + ret -= temp; > + else > + ret += temp; > > - return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; > + return ret; > } This decode schema is correct. Thanks, > > /* > @@ -279,6 +332,10 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) > printf("pll2: %dMHz\n", freq / 1000000); > freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK); > printf("pll3: %dMHz\n", freq / 1000000); > +#ifdef CONFIG_MX53 > + freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK); > + printf("pll4: %dMHz\n", freq / 1000000); > +#endif > printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK)); > printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK)); In fact, no one use PLL4 in u-boot. But I'm not against to put it in. > > diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h > index a4e680b..8a0f9e6 100644 > --- a/arch/arm/include/asm/arch-mx5/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h > @@ -100,6 +100,9 @@ > #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) > #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) > #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) > +#ifdef CONFIG_MX53 > +#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000) > +#endif > #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) > #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) > #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) > -- Tested on i.mx53evk, it outputs: MX53EVK U-Boot > clocks PLL1 800 MHz PLL2 400 MHz PLL3 216 MHz PLL4 594 MHz AHB 133333 kHz IPG 66666 kHz IPG PERCLK 20000 kHz Test-by: Jason Liu <Jason.hui@linaro.org> Jason Liu > 1.7.5.4 > >
On 09/22/2011 05:20 AM, Jason Hui wrote: > On Thu, Sep 15, 2011 at 8:09 AM, Marek Vasut <marek.vasut@gmail.com> wrote: >> The PLL decoding algorithm didn't take into account many configuration bits. >> Adjust it according to Linux kernel. Also, add PLL4 for MX53. >> >> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> >> --- >> arch/arm/cpu/armv7/mx5/clock.c | 77 ++++++++++++++++++++++++++---- >> arch/arm/include/asm/arch-mx5/imx-regs.h | 3 + >> 2 files changed, 70 insertions(+), 10 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c >> index 00610a0..9f37f7f 100644 >> --- a/arch/arm/cpu/armv7/mx5/clock.c >> +++ b/arch/arm/cpu/armv7/mx5/clock.c >> @@ -29,11 +29,13 @@ >> #include <asm/arch/imx-regs.h> >> #include <asm/arch/crm_regs.h> >> #include <asm/arch/clock.h> >> +#include <div64.h> >> >> enum pll_clocks { >> PLL1_CLOCK = 0, >> PLL2_CLOCK, >> PLL3_CLOCK, >> + PLL4_CLOCK, >> PLL_CLOCKS, >> }; >> >> @@ -41,25 +43,76 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { >> [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR, >> [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR, >> [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR, >> +#ifdef CONFIG_MX53 >> + [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR, >> +#endif >> }; >> >> +#define MXC_DPLLC_CTL_HFSM (1 << 7) >> +#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) >> + >> +#define MXC_DPLLC_OP_PDF_MASK 0xf >> +#define MXC_DPLLC_OP_MFI_MASK (0xf << 4) >> +#define MXC_DPLLC_OP_MFI_OFFSET 4 >> + >> +#define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff >> + >> +#define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff > > Can we put this stuff to crm_reg.h file? Right. Clock related defines are in the crm_reg.h file Best regards, Stefano Babic
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index 00610a0..9f37f7f 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -29,11 +29,13 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> +#include <div64.h> enum pll_clocks { PLL1_CLOCK = 0, PLL2_CLOCK, PLL3_CLOCK, + PLL4_CLOCK, PLL_CLOCKS, }; @@ -41,25 +43,76 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR, [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR, [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR, +#ifdef CONFIG_MX53 + [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR, +#endif }; +#define MXC_DPLLC_CTL_HFSM (1 << 7) +#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) + +#define MXC_DPLLC_OP_PDF_MASK 0xf +#define MXC_DPLLC_OP_MFI_MASK (0xf << 4) +#define MXC_DPLLC_OP_MFI_OFFSET 4 + +#define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff + +#define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; /* - * Calculate the frequency of this pll. + * Calculate the frequency of PLLn. */ -static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq) +static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) { - u32 mfi, mfn, mfd, pd; + uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret; + uint64_t refclk, temp; + int32_t mfn_abs; + + ctrl = readl(&pll->ctrl); + + if (ctrl & MXC_DPLLC_CTL_HFSM) { + mfn = __raw_readl(&pll->hfs_mfn); + mfd = __raw_readl(&pll->hfs_mfd); + op = __raw_readl(&pll->hfs_op); + } else { + mfn = __raw_readl(&pll->mfn); + mfd = __raw_readl(&pll->mfd); + op = __raw_readl(&pll->op); + } - mfn = __raw_readl(&pll->mfn); - mfd = __raw_readl(&pll->mfd) + 1; - mfi = __raw_readl(&pll->op); - pd = (mfi & 0xF) + 1; - mfi = (mfi >> 4) & 0xF; - mfi = (mfi >= 5) ? mfi : 5; + mfd &= MXC_DPLLC_MFD_MFD_MASK; + mfn &= MXC_DPLLC_MFN_MFN_MASK; + pdf = op & MXC_DPLLC_OP_PDF_MASK; + mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET; + + /* 21.2.3 */ + if (mfi < 5) + mfi = 5; + + /* Sign extend */ + if (mfn >= 0x04000000) { + mfn |= 0xfc000000; + mfn_abs = -mfn; + } else + mfn_abs = mfn; + + refclk = infreq * 2; + if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN) + refclk *= 2; + + refclk /= pdf + 1; + temp = refclk * mfn_abs; + do_div(temp, mfd + 1); + ret = refclk * mfi; + + if ((int)mfn < 0) + ret -= temp; + else + ret += temp; - return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; + return ret; } /* @@ -279,6 +332,10 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("pll2: %dMHz\n", freq / 1000000); freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK); printf("pll3: %dMHz\n", freq / 1000000); +#ifdef CONFIG_MX53 + freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK); + printf("pll4: %dMHz\n", freq / 1000000); +#endif printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK)); printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK)); diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index a4e680b..8a0f9e6 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -100,6 +100,9 @@ #define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) #define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) #define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) +#ifdef CONFIG_MX53 +#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000) +#endif #define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
The PLL decoding algorithm didn't take into account many configuration bits. Adjust it according to Linux kernel. Also, add PLL4 for MX53. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> --- arch/arm/cpu/armv7/mx5/clock.c | 77 ++++++++++++++++++++++++++---- arch/arm/include/asm/arch-mx5/imx-regs.h | 3 + 2 files changed, 70 insertions(+), 10 deletions(-)