Message ID | 1565788721-21866-4-git-send-email-philippe.reynes@softathome.com |
---|---|
State | Accepted |
Commit | b47f4891e5dded550f1eaee7daaac55b8c0bd76e |
Delegated to: | Tom Rini |
Headers | show |
Series | [U-Boot,V3,01/10] spi: hsspi: allow to be used on bcm6858 and bcm63158 | expand |
On Wed, Aug 14, 2019 at 03:18:35PM +0200, Philippe Reynes wrote: > From: Kursad Oney <kursad.oney@broadcom.com> > > The Broadcom ARM implementations do not yet have a clock framework so > one can use a fixed clock as the root clock of the hsspi block. The > fixed clock does not have an "enable" routine, since it's always > enabled. So when we hit this issue, getting an ENOSYS return, do not > bail but continue initialization. > > Similarly the block might already have been out of reset, say, when > we are booting from a SPI device. So if the reset signal is not configured > in the device tree, do not bail out and instead skip deasserting the reset. > > Signed-off-by: Kursad Oney <kursad.oney@broadcom.com> > Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com> Applied to u-boot/master, thanks!
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c index 7306531..e82b80c 100644 --- a/drivers/spi/bcm63xx_hsspi.c +++ b/drivers/spi/bcm63xx_hsspi.c @@ -349,32 +349,31 @@ static int bcm63xx_hsspi_probe(struct udevice *dev) return ret; ret = clk_enable(&clk); - if (ret < 0) + if (ret < 0 && ret != -ENOSYS) return ret; ret = clk_free(&clk); - if (ret < 0) + if (ret < 0 && ret != -ENOSYS) return ret; /* get clock rate */ ret = clk_get_by_name(dev, "pll", &clk); - if (ret < 0) + if (ret < 0 && ret != -ENOSYS) return ret; priv->clk_rate = clk_get_rate(&clk); ret = clk_free(&clk); - if (ret < 0) + if (ret < 0 && ret != -ENOSYS) return ret; /* perform reset */ ret = reset_get_by_index(dev, 0, &rst_ctl); - if (ret < 0) - return ret; - - ret = reset_deassert(&rst_ctl); - if (ret < 0) - return ret; + if (ret >= 0) { + ret = reset_deassert(&rst_ctl); + if (ret < 0) + return ret; + } ret = reset_free(&rst_ctl); if (ret < 0)