From patchwork Wed Aug 14 10:43:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1146946 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 467mSc0QwVz9sN1 for ; Wed, 14 Aug 2019 20:45:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727732AbfHNKpO (ORCPT ); Wed, 14 Aug 2019 06:45:14 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:6368 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727484AbfHNKpN (ORCPT ); Wed, 14 Aug 2019 06:45:13 -0400 X-UUID: 90cef1fb6b2c4dc8afdba457a633c001-20190814 X-UUID: 90cef1fb6b2c4dc8afdba457a633c001-20190814 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 1035860045; Wed, 14 Aug 2019 18:45:05 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 14 Aug 2019 18:45:05 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 14 Aug 2019 18:45:05 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , "sam shih" Subject: [PATCH v2 8/10] pwm: mediatek: add new property and fix mt7628 pwm Date: Wed, 14 Aug 2019 18:43:38 +0800 Message-ID: <1565779497-23621-1-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <621e49c01b943edb6ddac9182f34719eb0727f01.1548313019.git.ryder.lee@mediatek.com> References: <621e49c01b943edb6ddac9182f34719eb0727f01.1548313019.git.ryder.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: sam shih This fix mt7628 pwm during configure from userspace. The SoC is legacy MIPS and has no complex clock tree. This patch add property clock-frequency to the SoC specific data and legacy MIPS SoC need to configure it in DT. This property is use for period calculation. Signed-off-by: Sam Shih --- drivers/pwm/pwm-mediatek.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index d696df7a58fa..922a7543a2b1 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -53,6 +53,7 @@ struct pwm_mediatek_chip { struct clk *clk_top; struct clk *clk_main; struct clk **clk_pwms; + unsigned int clock_frequency; const struct pwm_mediatek_of_data *soc; }; @@ -139,7 +140,10 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, /* Using resolution in picosecond gets accuracy higher */ resolution = (u64)NSEC_PER_SEC * 1000; - do_div(resolution, clk_get_rate(clk)); + if (pc->soc->has_clks) + do_div(resolution, clk_get_rate(clk)); + else + do_div(resolution, pc->clock_frequency); cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); while (cnt_period > 8191) { @@ -216,6 +220,7 @@ static int pwm_mediatek_probe(struct platform_device *pdev) struct pwm_mediatek_chip *pc; struct resource *res; unsigned int npwms; + unsigned int clock_frequency; int ret; pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); @@ -265,6 +270,14 @@ static int pwm_mediatek_probe(struct platform_device *pdev) if (IS_ERR(pc->clk_pwms[i])) return PTR_ERR(pc->clk_pwms[i]); } + } else { + ret = of_property_read_u32(np, "clock-frequency", + &clock_frequency); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get clock_frequency\n"); + return ret; + } + pc->clock_frequency = clock_frequency; } platform_set_drvdata(pdev, pc);