From patchwork Wed Aug 14 09:23:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1146866 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506896-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="LiqCKUIr"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 467kf94z1hz9s7T for ; Wed, 14 Aug 2019 19:23:27 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=XKmk4zRCmLzbe5CNk4adHrSZYpb8hDTqMbqh80Sd8uFTw2nYAD 3vxsghn7zw7poNI0ZIgynYs+gg69LoBD320nG+esJwOqUb8vEoOwp4NFQ/OEyGzs vrdvZed7tyin9G0GIymX/EVFDf6iF3rvNYfyxF52DkiQe83091UXaohfQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=fTF5845hQFQ2ctmEMztmEX0tJIw=; b=LiqCKUIrsJz3A6nHif0I ffAEmNIUG1qRekQ5ZSe42J9Xsq5gPNG+7rkKITW1IUK9cTEqZy+PglQCZ+lO/gi0 X5yPpi/TZOmz94fRYfcMfhX0h6/QjkgHLKPr4dLMVFWtuVZoaDJUbzpQLDrsDtA+ oDvj5KSlLQmjIWjQ8kenuUM= Received: (qmail 58010 invoked by alias); 14 Aug 2019 09:23:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 57995 invoked by uid 89); 14 Aug 2019 09:23:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 14 Aug 2019 09:23:18 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 300E9360; Wed, 14 Aug 2019 02:23:17 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B02163F694; Wed, 14 Aug 2019 02:23:16 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, Kugan Vivekanandarajah , richard.sandiford@arm.com Cc: Kugan Vivekanandarajah Subject: [committed][AArch64] Use SVE MOV /M of scalars Date: Wed, 14 Aug 2019 10:23:15 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes This patch uses MOV /M to optimise selects between a duplicated scalar variable and a vector. Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. Applied as r274442. Richard 2019-08-14 Richard Sandiford Kugan Vivekanandarajah gcc/ * config/aarch64/aarch64-sve.md (*aarch64_sel_dup): New pattern. gcc/testsuite/ * g++.target/aarch64/sve/dup_sel_1.C: New test. * g++.target/aarch64/sve/dup_sel_2.C: Likewise. * g++.target/aarch64/sve/dup_sel_3.C: Likewise. * g++.target/aarch64/sve/dup_sel_4.C: Likewise. * g++.target/aarch64/sve/dup_sel_5.C: Likewise. * g++.target/aarch64/sve/dup_sel_6.C: Likewise. Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-08-14 10:18:10.634319267 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-08-14 10:20:21.241360707 +0100 @@ -3070,6 +3070,29 @@ (define_insn "*vcond_mask_" [(set_attr "movprfx" "*,*,*,*,yes,yes,yes")] ) +;; Optimize selects between a duplicated scalar variable and another vector, +;; the latter of which can be a zero constant or a variable. Treat duplicates +;; of GPRs as being more expensive than duplicates of FPRs, since they +;; involve a cross-file move. +(define_insn "*aarch64_sel_dup" + [(set (match_operand:SVE_ALL 0 "register_operand" "=?w, w, ??w, ?&w, ??&w, ?&w") + (unspec:SVE_ALL + [(match_operand: 3 "register_operand" "Upa, Upa, Upl, Upl, Upl, Upl") + (vec_duplicate:SVE_ALL + (match_operand: 1 "register_operand" "r, w, r, w, r, w")) + (match_operand:SVE_ALL 2 "aarch64_simd_reg_or_zero" "0, 0, Dz, Dz, w, w")] + UNSPEC_SEL))] + "TARGET_SVE" + "@ + mov\t%0., %3/m, %1 + mov\t%0., %3/m, %1 + movprfx\t%0., %3/z, %0.\;mov\t%0., %3/m, %1 + movprfx\t%0., %3/z, %0.\;mov\t%0., %3/m, %1 + movprfx\t%0, %2\;mov\t%0., %3/m, %1 + movprfx\t%0, %2\;mov\t%0., %3/m, %1" + [(set_attr "movprfx" "*,*,yes,yes,yes,yes")] +) + ;; ------------------------------------------------------------------------- ;; ---- [INT,FP] Compare and select ;; ------------------------------------------------------------------------- Index: gcc/testsuite/g++.target/aarch64/sve/dup_sel_1.C =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/g++.target/aarch64/sve/dup_sel_1.C 2019-08-14 10:20:21.245360681 +0100 @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); + +void +foo (int32_t val) +{ + register vnx4si x asm ("z0"); + register vnx4si y asm ("z0"); + asm volatile ("" : "=w" (y)); + val += 1; + vnx4si z = { val, val, val, val, val, val, val, val }; + x = (vnx4si) { -1, 0, 0, -1, 0, -1, 0, -1 } ? z : y; + asm volatile ("" :: "w" (x)); +} + +/* { dg-final { scan-assembler {\tmov\tz0\.s, p[0-7]/m, w[0-9]+\n} } } */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ Index: gcc/testsuite/g++.target/aarch64/sve/dup_sel_2.C =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/g++.target/aarch64/sve/dup_sel_2.C 2019-08-14 10:20:21.245360681 +0100 @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); + +void +foo (int32_t val) +{ + register vnx4si x asm ("z0"); + register vnx4si y asm ("z1"); + asm volatile ("" : "=w" (y)); + val += 1; + vnx4si z = { val, val, val, val, val, val, val, val }; + x = (vnx4si) { -1, 0, 0, -1, 0, -1, 0, -1 } ? z : y; + asm volatile ("" :: "w" (x)); +} + +/* { dg-final { scan-assembler {\tmovprfx\tz0, z1\n\tmov\tz0\.s, p[0-7]/m, w[0-9]+\n} } } */ Index: gcc/testsuite/g++.target/aarch64/sve/dup_sel_3.C =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/g++.target/aarch64/sve/dup_sel_3.C 2019-08-14 10:20:21.245360681 +0100 @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); +typedef float vnx4sf __attribute__((vector_size(32))); + +void +foo (float val) +{ + register vnx4sf x asm ("z0"); + register vnx4sf y asm ("z0"); + asm volatile ("" : "=w" (y)); + vnx4sf z = { val, val, val, val, val, val, val, val }; + x = (vnx4si) { -1, 0, 0, -1, 0, -1, 0, -1 } ? z : y; + asm volatile ("" :: "w" (x)); +} + +/* { dg-final { scan-assembler {\tmov\tz0\.s, p[0-7]/m, s[0-9]+\n} } } */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ Index: gcc/testsuite/g++.target/aarch64/sve/dup_sel_4.C =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/g++.target/aarch64/sve/dup_sel_4.C 2019-08-14 10:20:21.245360681 +0100 @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); +typedef float vnx4sf __attribute__((vector_size(32))); + +void +foo (float val) +{ + register vnx4sf x asm ("z0"); + register vnx4sf y asm ("z1"); + asm volatile ("" : "=w" (y)); + vnx4sf z = { val, val, val, val, val, val, val, val }; + x = (vnx4si) { -1, 0, 0, -1, 0, -1, 0, -1 } ? z : y; + asm volatile ("" :: "w" (x)); +} + +/* { dg-final { scan-assembler {\tmovprfx\tz0, z1\n\tmov\tz0\.s, p[0-7]/m, s[0-9]+\n} } } */ Index: gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/g++.target/aarch64/sve/dup_sel_5.C 2019-08-14 10:20:21.245360681 +0100 @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); + +void +foo (int32_t val) +{ + register vnx4si x asm ("z0"); + val += 1; + vnx4si y = { val, val, val, val, val, val, val, val }; + x = (vnx4si) { -1, 0, 0, -1, 0, -1, 0, -1 } ? y : (vnx4si) { 0 }; + asm volatile ("" :: "w" (x)); +} + +/* { dg-final { scan-assembler {\tmovprfx\tz0\.s, p[0-7]/z, z0\.s\n\tmov\tz0\.s, p[0-7]/m, w[0-9]+\n} } } */ Index: gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/g++.target/aarch64/sve/dup_sel_6.C 2019-08-14 10:20:21.245360681 +0100 @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msve-vector-bits=256" } */ + +#include + +typedef int32_t vnx4si __attribute__((vector_size(32))); +typedef float vnx4sf __attribute__((vector_size(32))); + +void +foo (float val) +{ + register vnx4sf x asm ("z0"); + vnx4sf y = { val, val, val, val, val, val, val, val }; + x = (vnx4si) { -1, 0, 0, -1, 0, -1, 0, -1 } ? y : (vnx4sf) { 0 }; + asm volatile ("" :: "w" (x)); +} + +/* { dg-final { scan-assembler {\tmovprfx\tz0\.s, p[0-7]/z, z0\.s\n\tmov\tz0\.s, p[0-7]/m, s[0-9]+\n} } } */