From patchwork Wed Aug 14 08:12:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1146827 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506875-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ahEtCupU"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 467j572Y3cz9sDQ for ; Wed, 14 Aug 2019 18:13:14 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=A3VVCbb+ptfyt3z12pQxMUa8Z4niJhW8mkI37wPxdsIy6BCKrd yI44Q+cNAd9c8UPzW3APK5YPq6JLdKMSGHwApvKAjnzdvpLmRG1Z0FGr/1UFjUUp ZvpaEqNKLfoMF+deJr/EOyZHRPL6tocw/y++NGvgTywXwwlmGU5nlvVA0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=wOUbrzAor2X+SBsFW4A7FJp5FGc=; b=ahEtCupU8itntknqOQl0 hoZDOO77tG7sKD33zmQqGwhKENK5w0u3vNXBZIK7Dm2jgVESTXpMYbvsBtjWyINg tqN0Sk0LZotSgNle1OhGDRwjFfFlk2NK9h83lGQVK/FWttXZOuLidMNxmB8E6yWb sicXFWoIQvhHwMdwonKBF10= Received: (qmail 58213 invoked by alias); 14 Aug 2019 08:13:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 58189 invoked by uid 89); 14 Aug 2019 08:13:04 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 14 Aug 2019 08:13:02 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 128D21570; Wed, 14 Aug 2019 01:13:01 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 913A33F694; Wed, 14 Aug 2019 01:13:00 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, Kugan Vivekanandarajah , richard.sandiford@arm.com Cc: Kugan Vivekanandarajah Subject: [committed][AArch64] Use unspecs for remaining SVE FP binary ops Date: Wed, 14 Aug 2019 09:12:59 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes Another patch in the series to make the SVE FP patterns use unspecs, so that they can accurately describe cases in which the predicate isn't a PTRUE. Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. Applied as r274417. Richard 2019-08-14 Richard Sandiford Kugan Vivekanandarajah gcc/ * config/aarch64/aarch64-sve.md (add3, *add3) (sub3, *sub3, *fabd3, mul3, *mul3) (div3, *div3): Use SVE_COND_FP_* unspecs instead of rtx codes. (cond_, *cond__2, *cond__3) (*cond__any): Add the predicate to the SVE_COND_FP_* unspecs. Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-08-14 09:08:04.289334990 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-08-14 09:10:48.912115057 +0100 @@ -1963,7 +1963,8 @@ (define_expand "cond_" (unspec:SVE_F [(match_operand: 1 "register_operand") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand") + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand") (match_operand:SVE_F 3 "register_operand")] SVE_COND_FP_BINARY) (match_operand:SVE_F 4 "aarch64_simd_reg_or_zero")] @@ -1977,7 +1978,8 @@ (define_insn "*cond__2" (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand" "0, w") + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand" "0, w") (match_operand:SVE_F 3 "register_operand" "w, w")] SVE_COND_FP_BINARY) (match_dup 2)] @@ -1995,7 +1997,8 @@ (define_insn "*cond__3" (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand" "w, w") + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand" "w, w") (match_operand:SVE_F 3 "register_operand" "0, w")] SVE_COND_FP_BINARY) (match_dup 3)] @@ -2013,7 +2016,8 @@ (define_insn_and_rewrite "*cond_< (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl, Upl, Upl, Upl") (unspec:SVE_F - [(match_operand:SVE_F 2 "register_operand" "0, w, w, w, w") + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand" "0, w, w, w, w") (match_operand:SVE_F 3 "register_operand" "w, 0, w, w, w")] SVE_COND_FP_BINARY) (match_operand:SVE_F 4 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, 0, w")] @@ -2051,10 +2055,9 @@ (define_expand "add3" [(set (match_operand:SVE_F 0 "register_operand") (unspec:SVE_F [(match_dup 3) - (plus:SVE_F - (match_operand:SVE_F 1 "register_operand") - (match_operand:SVE_F 2 "aarch64_sve_float_arith_with_sub_operand"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SVE_F 1 "register_operand") + (match_operand:SVE_F 2 "aarch64_sve_float_arith_with_sub_operand")] + UNSPEC_COND_FADD))] "TARGET_SVE" { operands[3] = aarch64_ptrue_reg (mode); @@ -2066,10 +2069,9 @@ (define_insn_and_split "*add3" [(set (match_operand:SVE_F 0 "register_operand" "=w, w, w") (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (plus:SVE_F - (match_operand:SVE_F 2 "register_operand" "%0, 0, w") - (match_operand:SVE_F 3 "aarch64_sve_float_arith_with_sub_operand" "vsA, vsN, w"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SVE_F 2 "register_operand" "%0, 0, w") + (match_operand:SVE_F 3 "aarch64_sve_float_arith_with_sub_operand" "vsA, vsN, w")] + UNSPEC_COND_FADD))] "TARGET_SVE" "@ fadd\t%0., %1/m, %0., #%3 @@ -2098,10 +2100,9 @@ (define_expand "sub3" [(set (match_operand:SVE_F 0 "register_operand") (unspec:SVE_F [(match_dup 3) - (minus:SVE_F - (match_operand:SVE_F 1 "aarch64_sve_float_arith_operand") - (match_operand:SVE_F 2 "register_operand"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SVE_F 1 "aarch64_sve_float_arith_operand") + (match_operand:SVE_F 2 "register_operand")] + UNSPEC_COND_FSUB))] "TARGET_SVE" { operands[3] = aarch64_ptrue_reg (mode); @@ -2113,10 +2114,9 @@ (define_insn_and_split "*sub3" [(set (match_operand:SVE_F 0 "register_operand" "=w, w, w, w") (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl, Upl, Upl") - (minus:SVE_F - (match_operand:SVE_F 2 "aarch64_sve_float_arith_operand" "0, 0, vsA, w") - (match_operand:SVE_F 3 "aarch64_sve_float_arith_with_sub_operand" "vsA, vsN, 0, w"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SVE_F 2 "aarch64_sve_float_arith_operand" "0, 0, vsA, w") + (match_operand:SVE_F 3 "aarch64_sve_float_arith_with_sub_operand" "vsA, vsN, 0, w")] + UNSPEC_COND_FSUB))] "TARGET_SVE && (register_operand (operands[2], mode) || register_operand (operands[3], mode))" @@ -2147,10 +2147,12 @@ (define_insn "*fabd3" [(set (match_operand:SVE_F 0 "register_operand" "=w") (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl") - (minus:SVE_F - (match_operand:SVE_F 2 "register_operand" "0") - (match_operand:SVE_F 3 "register_operand" "w"))] - UNSPEC_COND_FABS))] + (unspec:SVE_F + [(match_dup 1) + (match_operand:SVE_F 2 "register_operand" "0") + (match_operand:SVE_F 3 "register_operand" "w")] + UNSPEC_COND_FSUB)] + UNSPEC_COND_FABS))] "TARGET_SVE" "fabd\t%0., %1/m, %2., %3." ) @@ -2167,10 +2169,9 @@ (define_expand "mul3" [(set (match_operand:SVE_F 0 "register_operand") (unspec:SVE_F [(match_dup 3) - (mult:SVE_F - (match_operand:SVE_F 1 "register_operand") - (match_operand:SVE_F 2 "aarch64_sve_float_mul_operand"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SVE_F 1 "register_operand") + (match_operand:SVE_F 2 "aarch64_sve_float_mul_operand")] + UNSPEC_COND_FMUL))] "TARGET_SVE" { operands[3] = aarch64_ptrue_reg (mode); @@ -2182,10 +2183,9 @@ (define_insn_and_split "*mul3" [(set (match_operand:SVE_F 0 "register_operand" "=w, w") (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl") - (mult:SVE_F - (match_operand:SVE_F 2 "register_operand" "%0, w") - (match_operand:SVE_F 3 "aarch64_sve_float_mul_operand" "vsM, w"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SVE_F 2 "register_operand" "%0, w") + (match_operand:SVE_F 3 "aarch64_sve_float_mul_operand" "vsM, w")] + UNSPEC_COND_FMUL))] "TARGET_SVE" "@ fmul\t%0., %1/m, %0., #%3 @@ -2212,9 +2212,9 @@ (define_expand "div3" [(set (match_operand:SVE_F 0 "register_operand") (unspec:SVE_F [(match_dup 3) - (div:SVE_F (match_operand:SVE_F 1 "register_operand") - (match_operand:SVE_F 2 "register_operand"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SVE_F 1 "register_operand") + (match_operand:SVE_F 2 "register_operand")] + UNSPEC_COND_FDIV))] "TARGET_SVE" { operands[3] = aarch64_ptrue_reg (mode); @@ -2226,9 +2226,9 @@ (define_insn "*div3" [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w") (unspec:SVE_F [(match_operand: 1 "register_operand" "Upl, Upl, Upl") - (div:SVE_F (match_operand:SVE_F 2 "register_operand" "0, w, w") - (match_operand:SVE_F 3 "register_operand" "w, 0, w"))] - UNSPEC_MERGE_PTRUE))] + (match_operand:SVE_F 2 "register_operand" "0, w, w") + (match_operand:SVE_F 3 "register_operand" "w, 0, w")] + UNSPEC_COND_FDIV))] "TARGET_SVE" "@ fdiv\t%0., %1/m, %0., %3.