From patchwork Wed Aug 14 08:09:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1146823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506874-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="a2ixO0nz"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 467j120nwkz9sNC for ; Wed, 14 Aug 2019 18:09:41 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=Oa0Cmug/DyNkkish9BxVAS+1b8uiwZj5+vNtnbp0bFpmOlODYh t8Yka4JrWkb+GQ7ACRic6SS2PGtNSF7vnuvRb9h/saguYjIk8m5HYmXWbwkp/1qi 0vw7eHN+xobzHg9o5iZ0Cw0juSed87rZ6phypDJAuBIz8IsT8XL1zM3Lo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=bPkNEWr4KbXuVjYjPiimT6cV1YU=; b=a2ixO0nzLaAc8lkInPIh 38ib8a+3QHFTku5/0f55GYOA67zt2YGLxLifipkwf4WlzctAHNtpgxXWONrU6F0Y kwV2HgL+vBXayIPoxyeV4XbVwd4evxc5m865Hf4Lkpva8QHQDar/t7umaqjWbRNL EshTyGUg2EDS1Rloiy9VcCk= Received: (qmail 107932 invoked by alias); 14 Aug 2019 08:09:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 107555 invoked by uid 89); 14 Aug 2019 08:09:33 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 14 Aug 2019 08:09:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 21856337; Wed, 14 Aug 2019 01:09:31 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A09033F694; Wed, 14 Aug 2019 01:09:30 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, Kugan Vivekanandarajah , richard.sandiford@arm.com Cc: Kugan Vivekanandarajah Subject: [committed][AArch64] Don't rely on REG_EQUAL notes to combine SVE BIC Date: Wed, 14 Aug 2019 09:09:29 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes This patch generalises the SVE BIC pattern so that it doesn't rely on REG_EQUAL notes. The danger with relying on the notes is that an optimisation could for example replace the original (not ...) note with an (unspec ... UNSPEC_MERGE_PTRUE) in which the predicate is a constant. That's a legitimate change and could even be useful in some situations. The patch also makes the operand order match the SVE operand order in both the vector and predicate BIC patterns, which makes things easier for the ACLE. Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. Applied as r274416. Richard 2019-08-14 Richard Sandiford Kugan Vivekanandarajah gcc/ * config/aarch64/aarch64-sve.md (bic3): Rename to... (*bic3): ...this. Match the form that an SVE inverse actually has, rather than relying on REG_EQUAL notes. Make the insn operand order match the SVE operand order. (*3): Make the insn operand order match the SVE operand order. Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-08-14 09:03:20.515438326 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-08-14 09:05:41.902390293 +0100 @@ -1779,15 +1779,20 @@ (define_insn "3" ;; - BIC ;; ------------------------------------------------------------------------- -;; REG_EQUAL notes on "not3" should ensure that we can generate -;; this pattern even though the NOT instruction itself is predicated. -(define_insn "bic3" +(define_insn_and_rewrite "*bic3" [(set (match_operand:SVE_I 0 "register_operand" "=w") (and:SVE_I - (not:SVE_I (match_operand:SVE_I 1 "register_operand" "w")) - (match_operand:SVE_I 2 "register_operand" "w")))] + (unspec:SVE_I + [(match_operand 3) + (not:SVE_I (match_operand:SVE_I 2 "register_operand" "w"))] + UNSPEC_MERGE_PTRUE) + (match_operand:SVE_I 1 "register_operand" "w")))] "TARGET_SVE" - "bic\t%0.d, %2.d, %1.d" + "bic\t%0.d, %1.d, %2.d" + "&& !CONSTANT_P (operands[3])" + { + operands[3] = CONSTM1_RTX (mode); + } ) ;; ------------------------------------------------------------------------- @@ -2451,11 +2456,11 @@ (define_insn "*3" [(set (match_operand:PRED_ALL 0 "register_operand" "=Upa") (and:PRED_ALL (NLOGICAL:PRED_ALL - (not:PRED_ALL (match_operand:PRED_ALL 2 "register_operand" "Upa")) - (match_operand:PRED_ALL 3 "register_operand" "Upa")) + (not:PRED_ALL (match_operand:PRED_ALL 3 "register_operand" "Upa")) + (match_operand:PRED_ALL 2 "register_operand" "Upa")) (match_operand:PRED_ALL 1 "register_operand" "Upa")))] "TARGET_SVE" - "\t%0.b, %1/z, %3.b, %2.b" + "\t%0.b, %1/z, %2.b, %3.b" ) ;; -------------------------------------------------------------------------