From patchwork Wed Sep 14 08:43:16 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 114641 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9F184B71D4 for ; Wed, 14 Sep 2011 20:52:20 +1000 (EST) Received: from localhost ([::1]:33792 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R3l5K-0001c9-E1 for incoming@patchwork.ozlabs.org; Wed, 14 Sep 2011 04:44:46 -0400 Received: from eggs.gnu.org ([140.186.70.92]:42585) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R3l3Z-0007Up-Rs for qemu-devel@nongnu.org; Wed, 14 Sep 2011 04:43:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R3l3J-0000bS-IE for qemu-devel@nongnu.org; Wed, 14 Sep 2011 04:42:57 -0400 Received: from cantor2.suse.de ([195.135.220.15]:36991 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R3l3J-0000aK-1a; Wed, 14 Sep 2011 04:42:41 -0400 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id B0C4D91C69; Wed, 14 Sep 2011 10:42:39 +0200 (CEST) From: Alexander Graf To: qemu-devel Developers Date: Wed, 14 Sep 2011 10:43:16 +0200 Message-Id: <1315989802-18753-53-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1315989802-18753-1-git-send-email-agraf@suse.de> References: <1315989802-18753-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Blue Swirl , qemu-ppc@nongnu.org, Stefan Hajnoczi , Aurelien Jarno Subject: [Qemu-devel] [PATCH 52/58] ppc405: use RAM_ADDR_FMT instead of %08lx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Stefan Hajnoczi The RAM_ADDR_FMT macro hides the type of ram_addr_t so that format strings can be safely used. Make sure to use RAM_ADDR_FMT so that the build works on 32-bit hosts with Xen enabled. Whether Xen should affect ppc TCG targets is questionable but a separate issue. Signed-off-by: Stefan Hajnoczi Signed-off-by: Alexander Graf --- hw/ppc405_boards.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index e6c8ac6..712a6be 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -213,7 +213,8 @@ static void ref405ep_init (ram_addr_t ram_size, sram_size = 512 * 1024; sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size); #ifdef DEBUG_BOARD_INIT - printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset); + printf("%s: register SRAM at offset " RAM_ADDR_FMT "\n", + __func__, sram_offset); #endif cpu_register_physical_memory(0xFFF00000, sram_size, sram_offset | IO_MEM_RAM); @@ -357,7 +358,7 @@ static void ref405ep_init (ram_addr_t ram_size, #ifdef DEBUG_BOARD_INIT printf("%s: Done\n", __func__); #endif - printf("bdloc %016lx\n", (unsigned long)bdloc); + printf("bdloc " RAM_ADDR_FMT "\n", bdloc); } static QEMUMachine ref405ep_machine = {